{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T16:30:49Z","timestamp":1783701049000,"version":"3.55.0"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001744","name":"International Science and Technology Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001744","id-type":"DOI","asserted-by":"publisher"}]},{"name":"CMU Data Storage Systems Center"},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1212962"],"award-info":[{"award-number":["1212962"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1320531"],"award-info":[{"award-number":["1320531"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Intel and Seagate"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Select. Areas Commun."],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/jsac.2016.2603608","type":"journal-article","created":{"date-parts":[[2016,8,26]],"date-time":"2016-08-26T14:24:05Z","timestamp":1472221445000},"page":"2294-2311","source":"Crossref","is-referenced-by-count":69,"title":["Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8006-1019","authenticated-orcid":false,"given":"Yixin","family":"Luo","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Saugata","family":"Ghose","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yu","family":"Cai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Erich F.","family":"Haratsch","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2015.7248349"},{"key":"ref38","author":"spiegel","year":"1992","journal-title":"Theory and Problems of Probability and Statistics"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2699866"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591594"},{"key":"ref31","first-page":"18","article-title":"Exploiting memory device wear-out dynamics to improve NAND flash memory system performance","author":"pan","year":"2011","journal-title":"Proc FAST"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/7.4.308"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/0-8176-4487-3_4"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.06.007"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.2014.7037159"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917558"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2244361"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2016.2584602"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"ref12","author":"gasior","year":"2015","journal-title":"The SSD Endurance Experiment They’re All Dead"},{"key":"ref13","article-title":"LDPC code concepts and performance on highdensity flash memory","author":"haratsch","year":"2014","journal-title":"Proc Flash Memory Summit"},{"key":"ref14","article-title":"Controller concepts for 1y\/1z nm and 3D NAND flash","author":"haratsch","year":"2015","journal-title":"Proc Flash Memory Summit"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2011.2162262"},{"key":"ref16","year":"2003","journal-title":"Failure Mechanisms and Models for Semiconductor Devices"},{"key":"ref17","article-title":"Advanced flash technology status, scaling trends & implications to enterprise SSD technology enablement","author":"jeong","year":"2012","journal-title":"Proc Flash Memory Summit"},{"key":"ref18","first-page":"61","article-title":"Lifetime improvement of NAND flash-based storage systems using dynamic program and erase scaling","author":"jeong","year":"2014","journal-title":"Proc FAST"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1214\/aoms\/1177729694"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNC.2013.6504218"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657034"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.2015.7416949"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056062"},{"key":"ref6","first-page":"140","article-title":"Error analysis and retention-aware error management for NAND flash memory","volume":"17","author":"cai","year":"2013","journal-title":"Intel Technol J"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCNC.2015.7069413"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378623"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.266"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2591994"},{"key":"ref2","first-page":"521","article-title":"Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis","author":"cai","year":"2012","journal-title":"Proc DATE"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.49"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.28"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2084450"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ALLERTON.2015.7447074"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"354","DOI":"10.1109\/TCSII.2014.2312640","article-title":"Realizing unequal error correction for NAND flash memory at minimal read latency overhead","volume":"61","author":"li","year":"2014","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2010.15"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2015.7208284"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2014.140508"},{"key":"ref23","article-title":"Optimizing NAND flashbased SSDs via retention relaxation","author":"liu","year":"2012","journal-title":"Proc FAST"},{"key":"ref44","first-page":"243","article-title":"LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives","author":"zhao","year":"2013","journal-title":"Proc FAST"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558857"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178130"},{"key":"ref25","author":"luo","year":"2016"}],"container-title":["IEEE Journal on Selected Areas in Communications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/49\/7587443\/07553566.pdf?arnumber=7553566","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:42:44Z","timestamp":1641987764000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7553566\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":44,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jsac.2016.2603608","relation":{},"ISSN":["0733-8716","1558-0008"],"issn-type":[{"value":"0733-8716","type":"print"},{"value":"1558-0008","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9]]}}}