{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T15:36:20Z","timestamp":1771515380125,"version":"3.50.1"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2002,7,1]],"date-time":"2002-07-01T00:00:00Z","timestamp":1025481600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2002,7]]},"DOI":"10.1109\/jssc.2002.1015692","type":"journal-article","created":{"date-parts":[[2002,11,7]],"date-time":"2002-11-07T19:41:04Z","timestamp":1036698064000},"page":"926-931","source":"Crossref","is-referenced-by-count":33,"title":["A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature"],"prefix":"10.1109","volume":"37","author":[{"family":"Yuyun Liao","sequence":"first","affiliation":[]},{"given":"D.B.","family":"Roberts","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.962279"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542315"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.52161"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref5","volume-title":"Intel Corporation","year":"2000"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1984.1156629"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.563678"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.509866"},{"key":"ref9","volume-title":"Principles of CMOS VLSI Design","author":"Weste","year":"1992"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.881197"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/21860\/01015692.pdf?arnumber=1015692","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,23]],"date-time":"2025-03-23T06:49:08Z","timestamp":1742712548000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1015692\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,7]]},"references-count":10,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2002,7]]}},"URL":"https:\/\/doi.org\/10.1109\/jssc.2002.1015692","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2002,7]]}}}