{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,8]],"date-time":"2024-07-08T05:20:27Z","timestamp":1720416027859},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2008,11,1]],"date-time":"2008-11-01T00:00:00Z","timestamp":1225497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/jssc.2008.2005435","type":"journal-article","created":{"date-parts":[[2008,11,26]],"date-time":"2008-11-26T14:48:46Z","timestamp":1227710926000},"page":"2464-2471","source":"Crossref","is-referenced-by-count":35,"title":["A 14 mW Fractional-<i>N<\/i> PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme"],"prefix":"10.1109","volume":"43","author":[{"given":"Mark A.","family":"Ferriss","sequence":"first","affiliation":[]},{"given":"Michael P.","family":"Flynn","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","author":"walker","year":"2003","journal-title":"Phase-Locking in High-Performance Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858754"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.800925"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/82.275664"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521436"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.938372"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.173100"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.872739"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.848214"},{"key":"ref19","author":"perrott","year":"0","journal-title":"CppSim Behavioral Simulation Package"},{"key":"ref4","author":"perrott","year":"1997","journal-title":"Techniques for high data rate modulation and low power operation of fractional-$N$ frequency synthesizers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/22.981283"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884829"},{"key":"ref5","first-page":"8\/1","article-title":"synthesiser review for pan-european digital cellular radio","author":"meyers","year":"1990","journal-title":"VLSI Implementations for Second Generation Digital Cordless and Mobile Telecommunication Systems IEE Colloquium on"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858750"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908763"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2003.1257111"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.229400"},{"key":"ref9","first-page":"353","article-title":"a 14 mw fractional- pll modulator with an enhanced digital phase detector and frequency switching scheme","author":"ferriss","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/4685413\/04685428.pdf?arnumber=4685428","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:24Z","timestamp":1638217704000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4685428\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":19,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2008.2005435","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2008,11]]}}}