{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,27]],"date-time":"2026-09-27T11:02:29Z","timestamp":1790506949502,"version":"4.1.0"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2009,4,1]],"date-time":"2009-04-01T00:00:00Z","timestamp":1238544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2009,4]]},"DOI":"10.1109\/jssc.2009.2014023","type":"journal-article","created":{"date-parts":[[2009,3,24]],"date-time":"2009-03-24T19:22:51Z","timestamp":1237922571000},"page":"1121-1129","source":"Crossref","is-referenced-by-count":108,"title":["Next Generation Intel\u00af Core\u2122 Micro-Architecture (Nehalem) Clocking"],"prefix":"10.1109","volume":"44","author":[{"given":"Nasser","family":"Kurd","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Praveen","family":"Mosalikanti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mark","family":"Neidengard","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jonathan","family":"Douglas","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rajesh","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.809519"},{"key":"ref11","article-title":"a low-jitter and precise multiphase delay-locked loop using shifted averaging vcdl","author":"chang","year":"2003","journal-title":"IEEE ISSCC Dig"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"},{"key":"ref13","year":"2008","journal-title":"DDR3 SDRAM Specification"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870925"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585952"},{"key":"ref6","year":"0","journal-title":"Duty cycle measurement circuit"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859879"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007150"},{"key":"ref7","article-title":"a 20 gb\/s forwarded clock transceiver in 90 nm cmos","author":"casper","year":"2006","journal-title":"IEEE ISSCC Dig"},{"key":"ref2","article-title":"the implementation of the 65 nm dual-core 64 b merom processor","author":"sakran","year":"2006","journal-title":"IEEE ISSCC Dig"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418914"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/4804954\/04804981.pdf?arnumber=4804981","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:43:46Z","timestamp":1633913026000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4804981\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,4]]},"references-count":13,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2009.2014023","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2009,4]]}}}