{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,3]],"date-time":"2024-07-03T23:11:39Z","timestamp":1720048299824},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2009,9,1]],"date-time":"2009-09-01T00:00:00Z","timestamp":1251763200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2009,9]]},"DOI":"10.1109\/jssc.2009.2025344","type":"journal-article","created":{"date-parts":[[2009,9,2]],"date-time":"2009-09-02T13:38:27Z","timestamp":1251898707000},"page":"2554-2567","source":"Crossref","is-referenced-by-count":3,"title":["Energy\u2013Performance Tunable Logic"],"prefix":"10.1109","volume":"44","author":[{"given":"Bita","family":"Nezamfar","sequence":"first","affiliation":[]},{"given":"Elad","family":"Alon","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","first-page":"138","article-title":"applications of on-chip samplers for test and measurement of integrated circuits","author":"ho","year":"1998","journal-title":"1998 Symp VLSI Circuits Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368755"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810053"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref13","first-page":"163","article-title":"dynamic <formula formulatype=\"inline\"><tex notation=\"tex\">${\\rm v}_{\\rm th}$<\/tex><\/formula> scaling scheme for active leakage power reduction","author":"kim","year":"2002","journal-title":"Proc Design Automation and Test in Europe Conf and Exhibition"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.987094"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/55.663538"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"116","DOI":"10.1145\/871506.871537","article-title":"optimal body bias selection for leakage improvement and process compensation over different technology generations","author":"neau","year":"2003","journal-title":"Proc 2003 Int Symp Low Power Electronics and Design (ISLPED)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1147\/rd.475.0525"},{"key":"ref18","first-page":"218","article-title":"threshold canceling logic (tcl): a post-cmos logic family scalable down to 0.02 <formula formulatype=\"inline\"><tex notation=\"tex\">$ \\mu\\hbox{m}$<\/tex><\/formula>","author":"kohno","year":"2000","journal-title":"IEEE Int Solid-State Circuits (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.800519"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2005.11"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1145\/280756.280790","article-title":"The simulation and evaluation of dynamic voltage scaling algorithms","author":"pering","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"key":"ref29","year":"0","journal-title":"Communication Report on a Recent FPGA Chip"},{"key":"ref5","year":"0","journal-title":"Intel Pentium M Processor on 90 nm process with 2-MB L2 Cache"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1109\/LPE.2000.155245","article-title":"design issues for dynamic voltage scaling","author":"burd","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817120"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref1","year":"0","journal-title":"Intel Celeron Processor 200 Sequence Datasheet (Voltage identification on page 18)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.953479"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/82.974792"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.98975"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1999.777267"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/92.784093"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320939"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1145\/313817.313920","article-title":"The design of a low energy FPGA","author":"george","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5226685\/05226760.pdf?arnumber=5226760","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:50:57Z","timestamp":1633909857000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5226760\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,9]]},"references-count":30,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2009.2025344","relation":{},"ISSN":["0018-9200"],"issn-type":[{"value":"0018-9200","type":"print"}],"subject":[],"published":{"date-parts":[[2009,9]]}}}