{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:17:16Z","timestamp":1772205436899,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2009,12,1]],"date-time":"2009-12-01T00:00:00Z","timestamp":1259625600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2009,12]]},"DOI":"10.1109\/jssc.2009.2031042","type":"journal-article","created":{"date-parts":[[2009,12,18]],"date-time":"2009-12-18T18:14:49Z","timestamp":1261160089000},"page":"3590-3602","source":"Crossref","is-referenced-by-count":66,"title":["A 20-Gb\/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition"],"prefix":"10.1109","volume":"44","author":[{"given":"Jri","family":"Lee","sequence":"first","affiliation":[]},{"given":"Ke-Chung","family":"Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"214","article-title":"a 2.75 gb\/s cmos clock recovery circuit with broad capture range","author":"anand","year":"2001","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.806284"},{"key":"ref12","author":"razavi","year":"2002","journal-title":"Design of Integrated Circuits for Optical Communications"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759287"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"2181","DOI":"10.1109\/JSSC.2003.818566","article-title":"a 40-gb\/s clock and data recovery circuit in 0.18-<formula formulatype=\"inline\"><tex notation=\"tex\">$\\mu{\\hbox {m}}$<\/tex><\/formula> cmos technology","volume":"38","author":"lee","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.872871"},{"key":"ref16","first-page":"142","article-title":"a 52 mhz and 155 mhz clock-recovery pll","author":"devito","year":"1991","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922719"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880610"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.897165"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.1985.1074356"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1049\/el:19750415"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006227"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.918913"},{"key":"ref8","year":"0","journal-title":"40 Gb\/s and 100 Gb\/s Ethernet Task Force"},{"key":"ref7","first-page":"358","article-title":"a 40 gb\/s multi-data-rate cmos transceiver chipset with sfi-5 interface for optical transmission systems","author":"amamiya","year":"2009","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.868047"},{"key":"ref1","article-title":"mm-wave ic design: the transition from iii-v to cmos circuit techniques, short course, rf and high speed cmos","author":"yue","year":"2006","journal-title":"Proc IEEE Compound Semiconductor Integrated Circuit Symp (CSICS)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.173101"},{"key":"ref20","author":"razavi","year":"1995","journal-title":"Principles of Data Conversion System Design"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346583"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916598"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880617"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884389"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5342337\/05342361.pdf?arnumber=5342361","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:15Z","timestamp":1633909935000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5342361\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12]]},"references-count":24,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2009.2031042","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,12]]}}}