{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T08:07:54Z","timestamp":1767773274034},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/jssc.2009.2038127","type":"journal-article","created":{"date-parts":[[2010,2,12]],"date-time":"2010-02-12T14:28:54Z","timestamp":1265984934000},"page":"314-321","source":"Crossref","is-referenced-by-count":30,"title":["A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO"],"prefix":"10.1109","volume":"45","author":[{"family":"Wei Liu","sequence":"first","affiliation":[]},{"family":"Wei Li","sequence":"additional","affiliation":[]},{"family":"Peng Ren","sequence":"additional","affiliation":[]},{"family":"Chinglong Lin","sequence":"additional","affiliation":[]},{"family":"Shengdong Zhang","sequence":"additional","affiliation":[]},{"family":"Yangyuan Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807405"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858754"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2004.842067"},{"key":"ref11","first-page":"488","article-title":"a pvt tolerant 0.18 mhz to 600 mhz self-calibrated digital pll in 90 nm cmos process","volume":"541","author":"lin","year":"2004","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818298"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822780"},{"key":"ref7","author":"oppenheim","year":"1997","journal-title":"Signals and Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.375961"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801607"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5405130\/05405141.pdf?arnumber=5405141","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:43Z","timestamp":1633913143000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5405141\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":12,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2009.2038127","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2]]}}}