{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,12]],"date-time":"2024-06-12T00:08:42Z","timestamp":1718150922338},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/jssc.2010.2051262","type":"journal-article","created":{"date-parts":[[2010,8,24]],"date-time":"2010-08-24T18:54:22Z","timestamp":1282676062000},"page":"1856-1869","source":"Crossref","is-referenced-by-count":10,"title":["A High-Speed Low-Power Multi-VDD CMOS\/SIMOX SRAM With LV-TTL Level Input\/Output Pins\u2014Write\/Read Assist Techniques for 1-V Operated Memory Cells"],"prefix":"10.1109","volume":"45","author":[{"given":"Nobutaro","family":"Shibata","sequence":"first","affiliation":[]},{"given":"Mayumi","family":"Watanabe","sequence":"additional","affiliation":[]},{"given":"Hideomi","family":"Okiyama","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346591"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2005.1469356"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/4.705360"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.869786"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014015"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1051983"},{"key":"ref34","first-page":"282","article-title":"64 mb mobile stacked single-crystal si sram with selective dual pumping scheme and multi cell burn-in scheme for high density and low power sram","author":"an","year":"2004","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1997.585264"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.871315"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.953481"},{"key":"ref13","first-page":"5","author":"shibata","year":"2004","journal-title":"Writing circuitry for current-sensed multi-VDD SRAMs low-power writing operation with divided bitline scheme"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref15","first-page":"2056","article-title":"current-sensed sram techniques for megabit-class integration: progress in operating frequency by using hidden writing-recovery architecture","volume":"e82 c","author":"shibata","year":"1999","journal-title":"IEICE Trans Electron"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006433"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005813"},{"key":"ref18","first-page":"94","article-title":"megabit-class size-configurable 250-mhz sram macrocells with a squashed memory-cell architecture","volume":"e82 c","author":"shibata","year":"1999","journal-title":"IEICE Trans Electron"},{"key":"ref19","first-page":"1641","article-title":"high-performance memory macrocells with row and column sliceable architecture","volume":"e76 c","author":"shibata","year":"1993","journal-title":"IEICE Trans Electron"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705287"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004534"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.75053"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542318"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034076"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014015"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910963"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/el:19780397"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.766821"},{"key":"ref2","first-page":"200","article-title":"an 18-mb, 12.3-gb\/s cmos pipeline-burst cache sram with 1.54 gb\/s\/pin","author":"zhao","year":"1999","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.328631"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672528"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705286"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586011"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864124"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.891648"},{"key":"ref25","first-page":"1598","article-title":"a switched virtual-gnd level technique for fast and low power sram's","volume":"e80 c","author":"shibata","year":"1997","journal-title":"IEICE Trans Electron"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5556407\/05556423.pdf?arnumber=5556423","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:46:07Z","timestamp":1633913167000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5556423\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":36,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2051262","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}