{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,9]],"date-time":"2026-06-09T01:48:33Z","timestamp":1780969713342,"version":"3.54.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2010,9,1]],"date-time":"2010-09-01T00:00:00Z","timestamp":1283299200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/jssc.2010.2053094","type":"journal-article","created":{"date-parts":[[2010,8,24]],"date-time":"2010-08-24T18:54:22Z","timestamp":1282676062000},"page":"1809-1821","source":"Crossref","is-referenced-by-count":158,"title":["Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector"],"prefix":"10.1109","volume":"45","author":[{"given":"Xiang","family":"Gao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eric A. M.","family":"Klumperink","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gerard","family":"Socci","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mounir","family":"Bohsali","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bram","family":"Nauta","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433841"},{"key":"ref11","author":"crawford","year":"1994","journal-title":"Frequency Synthesizer Design Handbook"},{"key":"ref12","author":"kroupa","year":"1973","journal-title":"Frequency Synthesis Theory Design and Applications"},{"key":"ref13","first-page":"103","article-title":"phase-locked dro uses a sampling phase detector","author":"puglia","year":"1993","journal-title":"Microwaves RF"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.815932"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.910482"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.900300"},{"key":"ref17","first-page":"139","article-title":"a 2.2 ghz sub-sampling pll with 0.16 ${\\hbox {ps}}_{\\rm rms}$<\/tex><\/formula> jitter and $-\\hbox{125dbc\/hz}$<\/tex><\/formula> in-band phase noise at 700 $\\mu{\\hbox {w}}$<\/tex><\/formula> loop-components power","author":"gao","year":"2010","journal-title":"Symp VLSI Circuits Dig"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2015816"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821784"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914283"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.5947"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"966","DOI":"10.1109\/JSSC.2006.870894","article-title":"A 1 MHz bandwidth 3.6 GHz 0.18 $\\mu{\\hbox {m}}$<\/tex><\/formula> CMOS fractional-N synthesizer utilizing a hybrid PFD\/DAC structure for reduced broadband phase noise","volume":"41","author":"meninger","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.991390"},{"key":"ref1","author":"vaucher","year":"2002","journal-title":"Architectures for RF Frequency Synthesizers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016701"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1862","DOI":"10.1109\/JSSC.2004.835833","article-title":"A 2.5–10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-$\\mu{\\hbox {m}}$<\/tex><\/formula> CMOS","volume":"39","author":"van de beek","year":"2004","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"354","DOI":"10.1109\/ISSCC.2003.1234332","article-title":"a direct conversion cmos transceiver for ieee 802.11a wlans","author":"zhang","year":"2003","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","first-page":"594","article-title":"a 6.25 ghz 1 v lc-pll in 0.13 $\\mu{\\hbox {m}}$<\/tex><\/formula> cmos","author":"gu","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.858322"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5556407\/05556453.pdf?arnumber=5556453","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:43:27Z","timestamp":1633913007000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5556453\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":25,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2053094","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,9]]}}}