{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T12:00:27Z","timestamp":1763726427709},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2010,12]]},"DOI":"10.1109\/jssc.2010.2076591","type":"journal-article","created":{"date-parts":[[2010,10,20]],"date-time":"2010-10-20T14:09:39Z","timestamp":1287583779000},"page":"2582-2590","source":"Crossref","is-referenced-by-count":72,"title":["A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter"],"prefix":"10.1109","volume":"45","author":[{"given":"Takashi","family":"Tokairin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mitsuji","family":"Okada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaki","family":"Kitsunezuka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tadashi","family":"Maeda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muneo","family":"Fukaishi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.858754"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.859587"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.28"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.819128"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref8","first-page":"188","article-title":"a 320 fs-rms-jitter and 300 khz-bw all-digital fractional-n pll with self-corrected tdc and fast temperature tacking loop for wimax\/wlan 11n","author":"chang","year":"2009","journal-title":"VLSI Symp Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585972"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039530"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2004.1320575"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5625049\/05604672.pdf?arnumber=5604672","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:50Z","timestamp":1633913150000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5604672\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":11,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2076591","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}