{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:12:45Z","timestamp":1774800765656,"version":"3.50.1"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/jssc.2010.2079450","type":"journal-article","created":{"date-parts":[[2010,11,10]],"date-time":"2010-11-10T21:13:19Z","timestamp":1289423599000},"page":"173-183","source":"Crossref","is-referenced-by-count":306,"title":["A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling"],"prefix":"10.1109","volume":"46","author":[{"given":"J","family":"Howard","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Dighe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S R","family":"Vangal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G","family":"Ruhl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Jain","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V","family":"Erraguntla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M","family":"Konow","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M","family":"Riepen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M","family":"Gries","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G","family":"Droege","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T","family":"Lund-Larsen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Steibl","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V K","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R","family":"Van Der Wijngaart","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.1999.805265"},{"key":"ref11","article-title":"the intel 48-core single-chip cloud computer (scc) processor: programmer's view","author":"mattson","year":"2010","journal-title":"Int Conf High Performance Computing"},{"key":"ref12","article-title":"a 60 mhz 50 w fine-grain package integrated vr powering a cpu from 3.3 v","author":"schrom","year":"2010","journal-title":"Applied Power Electronics Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"ref4","first-page":"202","article-title":"a 3.3 v 0.6 <formula formulatype=\"inline\"> <tex notation=\"tex\">$\\mu{\\hbox {m}}$<\/tex><\/formula> bicmos superscalar microprocessor","author":"schutz","year":"1994","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref3","article-title":"a 45 nm logic technology with high -<formula formulatype=\"inline\"><tex notation=\"tex\">$k+{\\rm metal}$<\/tex> <\/formula> gate transistors, strained silicon, 9 cu interconnect layers, 193 nm dry patterning, and 100% pb-free packaging","author":"mistry","year":"2007","journal-title":"IEDM Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/71.205650"},{"key":"ref5","article-title":"a 2 tb\/s 6<formula formulatype=\"inline\"> <tex notation=\"tex\">$\\,\\times\\,$<\/tex><\/formula>4 mesh network with dvfs and 2.3 tb\/s\/w router in 45 nm cmos","author":"salihundam","year":"2010","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","first-page":"58","article-title":"a family of 45 nm ia processors","author":"kumar","year":"2009","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref7","year":"2008","journal-title":"JEDEC Solid State Technology Association DDR3 SDRAM Specification"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.1998.658762"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"ref9","year":"1994","journal-title":"SHMEM Techn Note for C"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5673672\/05621843.pdf?arnumber=5621843","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:54Z","timestamp":1633913154000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5621843\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2079450","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,1]]}}}