{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T07:24:16Z","timestamp":1768029856829,"version":"3.49.0"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2011,1]]},"DOI":"10.1109\/jssc.2010.2080550","type":"journal-article","created":{"date-parts":[[2010,11,10]],"date-time":"2010-11-10T21:13:19Z","timestamp":1289423599000},"page":"184-193","source":"Crossref","is-referenced-by-count":107,"title":["Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor"],"prefix":"10.1109","volume":"46","author":[{"given":"S","family":"Dighe","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S R","family":"Vangal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P","family":"Aseron","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T","family":"Jacob","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K A","family":"Bowman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J","family":"Howard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J","family":"Tschanz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V","family":"Erraguntla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V K","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.40"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798265"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234322"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342758"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2008.5213921"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818291"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2001.945402"},{"key":"ref17","first-page":"657","article-title":"A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 <ref_formula> <tex Notation=\"TeX\">$\\mu{\\hbox {m}}2$<\/tex><\/ref_formula> SRAM cell","author":"bai","year":"2004","journal-title":"IEDM Tech Dig"},{"key":"ref18","article-title":"Energy efficient near threshold chip multiprocessing","author":"zhai","year":"0","journal-title":"Proc 2007 Int Symp Low Power Electron Design (ISLPED)"},{"key":"ref19","author":"held","year":"0","journal-title":"From a Few Cores to Many A Tera-scale Computing Research Overview"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1145\/1013235.1013265","article-title":"Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits","author":"calhoun","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0469"},{"key":"ref8","first-page":"77","article-title":"Dynamic power-performance adaptation of parallel computation on chip multiprocessors","author":"li","year":"2006","journal-title":"Proc 12th Int Symp High-Performance Computer Architecture 2006"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2006.4271854"},{"key":"ref20","article-title":"Variation in 45 nm and implications for 32 nm and beyond","author":"kuhn","year":"2009","journal-title":"2nd Int CMOS Variability Conf 2009"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5673672\/05621842.pdf?arnumber=5621842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,13]],"date-time":"2021-11-13T10:30:10Z","timestamp":1636799410000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5621842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1]]},"references-count":20,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2080550","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,1]]}}}