{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:48:36Z","timestamp":1761662916867},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/jssc.2010.2100270","type":"journal-article","created":{"date-parts":[[2011,1,28]],"date-time":"2011-01-28T19:46:49Z","timestamp":1296244009000},"page":"660-668","source":"Crossref","is-referenced-by-count":66,"title":["A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS"],"prefix":"10.1109","volume":"46","author":[{"given":"Mohammad","family":"Taherzadeh-Sani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anas A.","family":"Hamoui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"214","article-title":"A 90 nm CMOS 1.2 V 10b power and speed programmable pipelined ADC with 0.5 pJ\/conversion-step","author":"geelen","year":"2006","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"462","article-title":"a 92.5 mw 205 ms\/s 10b pipeline if adc implemented in 1.2 v\/3.3 v 0.13 <formula formulatype=\"inline\"><tex notation=\"tex\">$\\mu$<\/tex> <\/formula>m cmos","author":"hernes","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052246"},{"key":"ref6","first-page":"269","author":"gray","year":"2009","journal-title":"Analysis and Design of Analog Integrated Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.820254"},{"key":"ref5","first-page":"642","author":"baker","year":"2005","journal-title":"CMOS Circuit Design Layout and Simulation"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.894825"},{"key":"ref8","author":"johns","year":"1997","journal-title":"Analog Integrated Circuit Design"},{"key":"ref7","author":"razavi","year":"2001","journal-title":"Design of Analog CMOS Integrated Circuits"},{"key":"ref2","first-page":"382","article-title":"A reconfigurable 10&#x2013;12b 0.4&#x2013;44 MS\/s pipelined ADC with 0.35&#x2013;0.5 pJ\/step in 1.2 V 90 nm digital CMOS","author":"taherzadeh-sani","year":"2010","journal-title":"Proc IEEE European Solid-State Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1052012"},{"key":"ref1","author":"sansen","year":"2006","journal-title":"Analog Design Essentials"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5718244\/05703142.pdf?arnumber=5703142","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T06:18:26Z","timestamp":1640240306000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5703142\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":12,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2010.2100270","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}