{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T13:53:49Z","timestamp":1787061229697,"version":"build-2736575974"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/jssc.2011.2108133","type":"journal-article","created":{"date-parts":[[2011,2,18]],"date-time":"2011-02-18T12:44:13Z","timestamp":1298033053000},"page":"859-869","source":"Crossref","is-referenced-by-count":218,"title":["A SAR-Assisted Two-Stage Pipeline ADC"],"prefix":"10.1109","volume":"46","author":[{"given":"Chun C.","family":"Lee","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael P.","family":"Flynn","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"2669","DOI":"10.1109\/JSSC.2006.884231","article-title":"A 6-bit 600-MS\/s 5.3-mW asynchronous ADC in 0.13-<ref_formula><tex Notation=\"TeX\">$\\mu{\\hbox {m}}$<\/tex><\/ref_formula> CMOS","volume":"41","author":"chen","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref11","first-page":"246","article-title":"A 65 fJ\/conv.-step 0-to-50 Ms\/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS","author":"craninckx","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","first-page":"238","article-title":"An 820 <ref_formula><tex Notation=\"TeX\">$\\mu{\\hbox {W}}$<\/tex><\/ref_formula> 9b 40 MS\/s noise-tolerant dynamic-SAR ADC in a 90 nm digital CMOS process","author":"giannini","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"},{"key":"ref14","first-page":"239","article-title":"A 12b 50 MS\/s 3.5 mW SAR assisted 2-stage pipeline ADC","author":"lee","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/49.761034"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.121557"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.858760"},{"key":"ref18","article-title":"High-performance parallel-serial analog to digital converter with error correction","author":"gorbatenko","year":"1966","journal-title":"IEEE National Convention Record"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.826813"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/82.168943"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977320"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.819167"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.261994"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373493"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884330"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006309"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050629"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.972143"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/82.850419"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433829"},{"key":"ref21","first-page":"382","article-title":"A 0.06 <ref_formula><tex Notation=\"TeX\">${\\hbox {mm}}^{2}$<\/tex><\/ref_formula> 8.9b ENOB 40 MS\/s pipelined SAR ADC in 65 nm CMOS","author":"furuta","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.210039"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/9780470546772"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5738962\/05714725.pdf?arnumber=5714725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,23]],"date-time":"2021-12-23T10:57:54Z","timestamp":1640257074000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5714725\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":25,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2011.2108133","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}