{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,10]],"date-time":"2025-11-10T13:33:53Z","timestamp":1762781633775},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T00:00:00Z","timestamp":1301616000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/jssc.2011.2109440","type":"journal-article","created":{"date-parts":[[2011,3,15]],"date-time":"2011-03-15T15:01:57Z","timestamp":1300201317000},"page":"815-827","source":"Crossref","is-referenced-by-count":61,"title":["A Large $\\sigma $V$_{\\rm TH}$\/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme"],"prefix":"10.1109","volume":"46","author":[{"given":"Jui-Jen","family":"Wu","sequence":"first","affiliation":[]},{"given":"Yen-Huei","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Po-Wei","family":"Chou","sequence":"additional","affiliation":[]},{"given":"Chien-Yuan","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Hung-Jen","family":"Liao","sequence":"additional","affiliation":[]},{"given":"Ming-Bin","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Yuan-Hua","family":"Chu","sequence":"additional","affiliation":[]},{"given":"Wen-Chin","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Hiroyuki","family":"Yamauchi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/4.962296"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/4.705359"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.688077"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/4.726553"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342741"},{"key":"ref13","first-page":"105","article-title":"A 32 nm 8.3 GHz 64-entry x32b variation tolerant near-threshold voltage register file","author":"agarwal","year":"2010","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref15","first-page":"254","article-title":"A 45 nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R\/W access issues","author":"ishikura","year":"2007","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048496"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373427"},{"key":"ref19","first-page":"158","article-title":"A 45 nm 0.6 V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref28","article-title":"SRAM Tutorial","author":"yamauchi","year":"2009","journal-title":"IEEE ISSCC"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"ref27","first-page":"210","article-title":"A highly manufacturable 28 nm CMOS low power platform technology with fully functional 64 Mb SRAM using dual\/tripe gate oxide process","author":"wu","year":"2009","journal-title":"Symp VLSI Tech Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014009"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"1657","DOI":"10.1109\/TCSI.2008.2010101","article-title":"Wide embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems","volume":"56","author":"chang","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907998"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903072"},{"key":"ref7","first-page":"211","article-title":"A 45 nm dual-port SRAM with write and read capability enhancement at low voltage","author":"wang","year":"2007","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494078"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014208"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915499"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687516"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864124"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852159"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109440"},{"key":"ref26","year":"0","journal-title":"8T Low Leakage SRAM Cell"},{"key":"ref25","year":"1993","journal-title":"Multi-port SRAM"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/5738962\/05729345.pdf?arnumber=5729345","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:25Z","timestamp":1633909945000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5729345\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":33,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2011.2109440","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}