{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:50:07Z","timestamp":1768071007926,"version":"3.49.0"},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/jssc.2011.2167814","type":"journal-article","created":{"date-parts":[[2011,10,13]],"date-time":"2011-10-13T20:39:24Z","timestamp":1318538364000},"page":"194-205","source":"Crossref","is-referenced-by-count":23,"title":["A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor"],"prefix":"10.1109","volume":"47","author":[{"given":"Marcelo","family":"Yuffe","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moty","family":"Mehalel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ernest","family":"Knoll","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph","family":"Shor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsvika","family":"Kurts","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eran","family":"Altshuler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eyal","family":"Fayneh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kosta","family":"Luria","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Zelikson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2003.1221150"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034076"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537431"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669170"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537829"},{"key":"ref7","first-page":"221","article-title":"Temperature sensor design in a high volume manufacturing 65 nm CMOS digital process","author":"duarte","year":"2007","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref1","year":"0","journal-title":"Intel 64 and IA-32ArchitecturesOptimization Reference Manual"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6109882\/06044730.pdf?arnumber=6044730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:51Z","timestamp":1633909611000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6044730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":8,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2011.2167814","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,1]]}}}