{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,30]],"date-time":"2026-01-30T06:16:58Z","timestamp":1769753818464,"version":"3.49.0"},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2012,1]]},"DOI":"10.1109\/jssc.2011.2167823","type":"journal-article","created":{"date-parts":[[2011,10,27]],"date-time":"2011-10-27T20:14:07Z","timestamp":1319746447000},"page":"164-176","source":"Crossref","is-referenced-by-count":26,"title":["Design of the Two-Core x86-64 AMD \u201cBulldozer\u201d Module in 32 nm SOI CMOS"],"prefix":"10.1109","volume":"47","author":[{"given":"Hugh","family":"McIntyre","sequence":"first","affiliation":[]},{"given":"Srikanth","family":"Arekapudi","sequence":"additional","affiliation":[]},{"given":"Eric","family":"Busta","sequence":"additional","affiliation":[]},{"given":"Timothy","family":"Fischer","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Golden","sequence":"additional","affiliation":[]},{"given":"Aaron","family":"Horiuchi","sequence":"additional","affiliation":[]},{"given":"Tom","family":"Meneghini","sequence":"additional","affiliation":[]},{"given":"Samuel","family":"Naffziger","sequence":"additional","affiliation":[]},{"given":"James","family":"Vinh","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"162","DOI":"10.1109\/JSSC.2010.2080530","article-title":"An x86-64 core in 32 nm SOI CMOS","volume":"46","author":"jotwani","year":"2011","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746228"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"ref5","article-title":"Westmere: A family of 32 nm IA processors","author":"kurd","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699203"},{"key":"ref7","year":"2010","journal-title":"Advanced Configuration & Power Interface Specification Rev 4 0a"},{"key":"ref2","article-title":"Design solutions for the Bulldozer 32 nm SOI 2-core processor module in an 8-core CPU","author":"fischer","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1998.687985"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.23"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6109882\/06060836.pdf?arnumber=6060836","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:47Z","timestamp":1633909607000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6060836\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":9,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2011.2167823","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,1]]}}}