{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,6]],"date-time":"2025-10-06T06:07:28Z","timestamp":1759730848009},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/jssc.2012.2185180","type":"journal-article","created":{"date-parts":[[2012,2,13]],"date-time":"2012-02-13T22:01:02Z","timestamp":1329170462000},"page":"969-980","source":"Crossref","is-referenced-by-count":12,"title":["Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM"],"prefix":"10.1109","volume":"47","author":[{"given":"Yen-Huei","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shao-Yu","family":"Chou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Quincy","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Min","family":"Chan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dar","family":"Sun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hung-Jen","family":"Liao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ping","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroyuki","family":"Yamauchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007151"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912589"},{"key":"ref33","first-page":"354","article-title":"SRAM stability characterization using tunable ring oscillators in 45 nm CMOS","author":"tsai","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032698"},{"key":"ref31","first-page":"42","article-title":"Large-scale read\/write margin measurement in 45 nm CMOS SRAM arrays","author":"guo","year":"2008","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref30","first-page":"44","article-title":"Characterization of bit transistors in a functional SRAM","author":"deng","year":"2008","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/4.705359"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001937"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2008.2004329"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164300"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"1209","DOI":"10.1109\/JSSC.2009.2014208","article-title":"A 0.6 V dual-rail compiler SRAM design on 45 nm CMOS technology with adaptive SRAM power for lower VDD_min VLSIs","volume":"44","author":"chen","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref40","first-page":"941","article-title":"A 32 nm logic technology featuring 2nd-generation high-k metal-gate transistors, enhanced channel strain and 0.171 um<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$^{2}$<\/tex><\/formula> SRAM cell size in a 291 Mb array","author":"natarajan","year":"2008","journal-title":"IEEE Asia Solid-State Circuits Conf (ASSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2109440"},{"key":"ref13","first-page":"158","article-title":"A 45 nm 0.6 V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433816"},{"key":"ref15","first-page":"348","article-title":"A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149 um<formula formulatype=\"inline\"><tex Notation=\"TeX\">$^2$<\/tex><\/formula> cell in 32 nm high-K metal-gate CMOS","author":"fujimura","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433817"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494081"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.925405"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373427"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391522"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705289"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681601"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014009"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2091321"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907998"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903072"},{"key":"ref7","first-page":"211","article-title":"A 45 nm dual-port SRAM with write and read capability enhancement at low voltage","author":"wang","year":"2007","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494078"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342728"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001903"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"172","DOI":"10.1109\/JSSC.2007.907996","article-title":"A 1.1 GHz 12 uA\/Mb-leakage SRAM design in 65 nm ultra-low-power CMOS technology with integrated leakage reduction for mobile applications","volume":"43","author":"wang","year":"2008","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref42","doi-asserted-by":"crossref","first-page":"1657","DOI":"10.1109\/TCSI.2008.2010101","article-title":"Wide VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems","volume":"56","author":"chang","year":"2009","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2083130"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034082"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2065750"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342697"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332737"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6173080\/06151870.pdf?arnumber=6151870","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:53:27Z","timestamp":1633910007000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6151870\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":44,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2012.2185180","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,4]]}}}