{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,6]],"date-time":"2026-10-06T11:49:03Z","timestamp":1791287343456,"version":"4.1.0"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/jssc.2012.2192655","type":"journal-article","created":{"date-parts":[[2012,4,23]],"date-time":"2012-04-23T21:35:25Z","timestamp":1335216925000},"page":"1334-1343","source":"Crossref","is-referenced-by-count":26,"title":["A 10-b 320-MS\/s Stage-Gain-Error Self-Calibration Pipeline ADC"],"prefix":"10.1109","volume":"47","author":[{"given":"Chien-Jian","family":"Tseng","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hung-Wei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei-Ting","family":"Shen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei-Chih","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hsin-Shu","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831503"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032258"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332794"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.75065"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref15","first-page":"126","article-title":"A 10 b 320 MS\/s 40 mW open-loop interpolated pipeline ADC","author":"miyahara","year":"2011","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.821306"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031044"},{"key":"ref6","first-page":"462","article-title":"A 92.5 mW 205 MS\/s 10 b pipeline IF ADC implemented in 1.2 V\/3.3 V 0.13 <ref_formula><tex Notation=\"TeX\">$\\mu{\\hbox {m}}$<\/tex><\/ref_formula> CMOS","author":"hernes","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493976"},{"key":"ref8","first-page":"292","article-title":"A 16 b 250 MS\/s IF-sampling pipelined A\/D converter with background calibration","author":"ali","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","first-page":"276","article-title":"A 600 MS\/s 5-bit pipelined ADC for serial-link applications","author":"varzaghani","year":"2004","journal-title":"Dig Symp VLSI Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006312"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873862"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.173122"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6203507\/06188519.pdf?arnumber=6188519","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,11,14]],"date-time":"2017-11-14T07:15:29Z","timestamp":1510643729000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6188519\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":15,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2012.2192655","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,6]]}}}