{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,30]],"date-time":"2024-06-30T22:25:37Z","timestamp":1719786337821},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/jssc.2012.2211697","type":"journal-article","created":{"date-parts":[[2012,9,18]],"date-time":"2012-09-18T18:02:51Z","timestamp":1347991371000},"page":"2627-2642","source":"Crossref","is-referenced-by-count":6,"title":["An 8.0-Gb\/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors"],"prefix":"10.1109","volume":"47","author":[{"given":"Alvin L. S.","family":"Loke","sequence":"first","affiliation":[]},{"given":"Bruce A.","family":"Doyle","sequence":"additional","affiliation":[]},{"given":"Sanjeev K.","family":"Maheshwari","sequence":"additional","affiliation":[]},{"given":"Dennis M.","family":"Fischette","sequence":"additional","affiliation":[]},{"given":"Charles L.","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Tin Tin","family":"Wee","sequence":"additional","affiliation":[]},{"given":"Emerson S.","family":"Fang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280865"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/4.881205"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803048"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1049\/el:19750415"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.875289"},{"key":"ref37","first-page":"34","article-title":"A 5.2 Gbps HyperTransport&#x2122; integrated AC coupled receiver with DFR DC restore","author":"fang","year":"2007","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672163"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006230"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1985.1052381"},{"key":"ref10","year":"0","journal-title":"PCI Express 2 0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2167823"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.881207"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1681","DOI":"10.1109\/ACSSC.2003.1292271","article-title":"Modeling and mitigation of jitter in high-speed source-synchronous interchip communication systems","author":"balamurugan","year":"2003","journal-title":"Proc Asilomar Conf Signals Syst Comput"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1882486.1882513"},{"key":"ref15","first-page":"226","article-title":"Bridging design and manufacture of analog\/mixed-signal circuits in advanced CMOS","author":"feng","year":"2011","journal-title":"IEEE Symp VLSI Technol Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"440","DOI":"10.1147\/rd.275.0440","article-title":"A DC-balanced, partitioned-block, 8B\/10B transmission code","volume":"27","author":"widmer","year":"1983","journal-title":"IBM J Res Devel"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2007.21"},{"key":"ref18","first-page":"246","article-title":"A 45 nm SOI-CMOS dual-PLL processor clock system for multi-protocol I\/O","author":"fischette","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1998.689221"},{"key":"ref28","author":"walker","year":"2003","journal-title":"Phase-Locking in High-Performance Systems From Devices to Architectures"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014023"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055386"},{"key":"ref3","article-title":"The Opteron CMP NorthBridge architecture: Now and in the future","author":"conway","year":"2006","journal-title":"Proc IEEE Hot Chips V"},{"key":"ref6","article-title":"Blade computing with the AMD Opteron&#x2122; processor","author":"conway","year":"2007","journal-title":"Proc IEEE Hot Chips V"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.278348"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373608"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280778"},{"key":"ref7","article-title":"Bulldozer: A new approach to multithreaded compute performance","author":"butler","year":"2010","journal-title":"Proc IEEE Hot Chips V"},{"key":"ref2","year":"0","journal-title":"HyperTransport 3 1"},{"key":"ref9","year":"0","journal-title":"DDR3"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/40.653013"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1994.383301"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123620"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/6040.938294"},{"key":"ref24","first-page":"1158","article-title":"Transfer functions for the reference clock jitter in a serial link: Theory and applications","author":"li","year":"2004","journal-title":"Proc Int Test Conf"},{"key":"ref23","article-title":"Challenges in serial electrical interconnects at 5 to 10 Gb\/s and beyond","author":"beukema","year":"2007","journal-title":"IEEE Solid-State Circuits Society"},{"key":"ref26","author":"lee","year":"1998","journal-title":"The Design of CMOS Radio-Frequency Integrated Circuits"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077350"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6339059\/06305490.pdf?arnumber=6305490","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:44Z","timestamp":1633909904000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6305490\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":39,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2012.2211697","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}