{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:15:09Z","timestamp":1763468109446},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1109\/jssc.2012.2222814","type":"journal-article","created":{"date-parts":[[2012,12,31]],"date-time":"2012-12-31T19:09:04Z","timestamp":1356980944000},"page":"104-117","source":"Crossref","is-referenced-by-count":30,"title":["Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS"],"prefix":"10.1109","volume":"48","author":[{"given":"David","family":"Fick","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ronald G.","family":"Dreslinski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bharan","family":"Giridhar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gyouho","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sangwon","family":"Seo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Fojtik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudhir","family":"Satpathy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoonmyung","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daeyeon","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nurrachman","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Wieckowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gregory","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Trevor","family":"Mudge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Blaauw","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Sylvester","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","article-title":"ARM Cortex-A9","year":"0"},{"key":"ref30","article-title":"Tezzaron semiconductor octopus DRAM","year":"0"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024774"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176969"},{"key":"ref12","first-page":"190","article-title":"Centip3De: A 3930 dmips\/W configurable near-threshold 3D stacked system with 64 arm cortex-m3 cores","author":"fick","year":"0","journal-title":"IEEE ISSCC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609253"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283789"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433921"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007160"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746332"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336210"},{"key":"ref28","article-title":"OpenCores: Scan Based Serial Communication","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref27","article-title":"ARM Cortex-M3","year":"0"},{"key":"ref3","first-page":"88","article-title":"Tile64&#x2014;Processor: A 64-core SoC with mesh interconnect","author":"bell","year":"0","journal-title":"IEEE ISSCC 2008"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"453","DOI":"10.1145\/1394608.1382159","article-title":"3D-stacked memory architectures for multi-core processors","volume":"36","author":"loh","year":"2008","journal-title":"SIGARCH Comput Archit News"},{"key":"ref29","article-title":"Tezzaron semiconductor FaStack&#x00AE; technology","year":"0"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388564"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0126"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1412587.1412589"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176968"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034076"},{"key":"ref20","first-page":"148","article-title":"Drowsy caches: simple techniques for reducing leakage power","author":"flautner","year":"2002","journal-title":"Proc 29th Annual Int Symp Computer Architecture"},{"key":"ref22","first-page":"332","article-title":"A sub-200 mv 6T SRAM in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS","author":"zhai","year":"0","journal-title":"IEEE ISSCC 2007"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085970"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref23","first-page":"234","article-title":"Capacitive-coupling wordline boosting with self-induced Vcc collapse for write Vmin reduction in 22-nm 8T SRAM","author":"kulkarni","year":"0","journal-title":"2012 IEEE ISSCC"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917502"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147174"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6399535\/06399548.pdf?arnumber=6399548","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:50:47Z","timestamp":1633909847000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6399548\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":31,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2012.2222814","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,1]]}}}