{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T19:00:39Z","timestamp":1761418839112},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,4,1]],"date-time":"2013-04-01T00:00:00Z","timestamp":1364774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/jssc.2013.2237991","type":"journal-article","created":{"date-parts":[[2013,1,21]],"date-time":"2013-01-21T19:10:15Z","timestamp":1358795415000},"page":"1018-1030","source":"Crossref","is-referenced-by-count":89,"title":["A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement"],"prefix":"10.1109","volume":"48","author":[{"given":"Yu-Huei","family":"Lee","sequence":"first","affiliation":[]},{"given":"Shen-Yu","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Chao-Chang","family":"Chiu","sequence":"additional","affiliation":[]},{"given":"Alex Chun-Hsien","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Ke-Horng","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Ying-Hsi","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Shih-Wei","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Tsung-Yen","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Chen-Chih","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Chao-Cheng","family":"Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2007.904237"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2009.2030805"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2010.2101085"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917533"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.900281"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042251"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859886"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032493"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.962279"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818296"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.836353"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907175"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2007.911776"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"2735","DOI":"10.1109\/TPEL.2009.2030806","article-title":"Analysis and design of adaptive bus voltage positioning system for two-stage voltage regulators","volume":"24","author":"lee","year":"2009","journal-title":"IEEE Trans Power Electron"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2004.830034"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908769"},{"key":"ref28","first-page":"486","article-title":"13% power reduction in 16 b integer unit in 40 nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO","author":"hirairi","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196318"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123569"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063610"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880609"},{"key":"ref29","first-page":"442","article-title":"A 0.9 V 0.35 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> adaptively biased CMOS LDO regulator with fast transient response","author":"lam","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2211671"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2065610"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2027546"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822773"},{"key":"ref20","first-page":"178","article-title":"A 50 nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm CMOS for 5.6 times MIPS performance","author":"lee","year":"2012","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2005.869747"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2009.2032657"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2012.2191799"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.887472"},{"key":"ref26","first-page":"1","article-title":"0.5-V input digital LDO with 98.7% current efficiency and 2.7-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm A}$<\/tex><\/formula> quiescent current in 65 nm CMOS","author":"okuma","year":"2010","journal-title":"Proc IEEE Custom Integrated Circuits Conf (CICC)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885060"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6484888\/06416091.pdf?arnumber=6416091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:39Z","timestamp":1638217719000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6416091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2237991","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,4]]}}}