{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,3]],"date-time":"2025-05-03T07:22:47Z","timestamp":1746256967924},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,4,1]],"date-time":"2013-04-01T00:00:00Z","timestamp":1364774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/jssc.2013.2239092","type":"journal-article","created":{"date-parts":[[2013,1,28]],"date-time":"2013-01-28T19:01:41Z","timestamp":1359399701000},"page":"932-939","source":"Crossref","is-referenced-by-count":50,"title":["A 32 nm 0.58-fJ\/Bit\/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation"],"prefix":"10.1109","volume":"48","author":[{"given":"Igor","family":"Arsovski","sequence":"first","affiliation":[]},{"given":"Travis","family":"Hebig","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Dobson","sequence":"additional","affiliation":[]},{"given":"Reid","family":"Wistort","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.726560"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837979"},{"key":"ref10","first-page":"102","article-title":"a new method for improved delay characterization of vlsi logic","author":"wagner","year":"1982","journal-title":"ESSCIRC '82 Eighth European Solid-State Circuits Conference ESSCIRC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.621492"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"926","DOI":"10.1109\/ISCAS.2001.922390","article-title":"Power modeling and low-power design of content addressable memories","volume":"4","author":"hsiao","year":"2001","journal-title":"Proc IEEE Int Symp Circuits and Systems ISCAS 2001"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818139"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320819"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2082270"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568702"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2163205"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4\/6484888\/06422330.pdf?arnumber=6422330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:39Z","timestamp":1638217719000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6422330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":10,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2239092","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,4]]}}}