{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:16:02Z","timestamp":1763468162790},"reference-count":7,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2013,8,1]],"date-time":"2013-08-01T00:00:00Z","timestamp":1375315200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1109\/jssc.2013.2258815","type":"journal-article","created":{"date-parts":[[2013,7,19]],"date-time":"2013-07-19T18:04:22Z","timestamp":1374257062000},"page":"1954-1962","source":"Crossref","is-referenced-by-count":25,"title":["An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel\u00ae Xeon\u00ae Processor E5 Family"],"prefix":"10.1109","volume":"48","author":[{"family":"Min Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moty","family":"Mehalel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramesh","family":"Arvapalli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Songnian He","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"ref3","first-page":"456","article-title":"A 4.0 GHz 291 Mb voltage-scalable SRAM design in 32 nm high-K metal-gate CMOS with integrated power management","author":"wang","year":"2009","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref6","first-page":"74","article-title":"A 32 nm westmere-ex Xeon\ufffd enterprise processor","author":"sawant","year":"2011","journal-title":"Proc IEEE ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"152","article-title":"A 45 nm 24 MB On-Die L3 cache for the 8-Core multi-threaded Xeon\ufffd processor","author":"chang","year":"2009","journal-title":"Proc Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","article-title":"An energy efficient 32 nm 20 MB L3 cache for Intel\ufffd Xeon\ufffd processor E5 family","author":"huang","year":"2012","journal-title":"IEEE CICC"},{"key":"ref2","first-page":"659","article-title":"High performance 32 nm logic technology featuring 2nd generation high-k+ metal gate transistors","author":"packan","year":"2009","journal-title":"Proc IEDM Tech Dig"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2167814"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6564404\/06515193.pdf?arnumber=6515193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:41Z","timestamp":1638217721000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6515193\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":7,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2258815","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,8]]}}}