{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T08:29:07Z","timestamp":1769848147788,"version":"3.49.0"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/jssc.2013.2264618","type":"journal-article","created":{"date-parts":[[2013,6,27]],"date-time":"2013-06-27T18:02:16Z","timestamp":1372356136000},"page":"2118-2127","source":"Crossref","is-referenced-by-count":19,"title":["A 5 Gb\/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation"],"prefix":"10.1109","volume":"48","author":[{"family":"Seon-Kyoo Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Byungsub Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hong-June Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jae-Yoon Sim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/81.242323"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"552","DOI":"10.1109\/TADVP.2009.2033938","article-title":"Serpentine microstrip lines with zero far-end crosstalk for parallel high-speed DRAM interfaces","volume":"33","author":"lee","year":"2010","journal-title":"IEEE Trans Adv Packag"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/el:20083043"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028917"},{"key":"ref14","first-page":"140","article-title":"4x 12 Gb\/s 0.96 pJ\/b\/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I\/Os in 65 nm CMOS","author":"oh","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref15","first-page":"140","article-title":"A 5 Gb\/s single-ended parallel receiver with adaptive FEXT cancellation","author":"lee","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.962286"},{"key":"ref17","first-page":"446","article-title":"A 15 Gb\/s 0.5 mW\/Gb\/s 2-tap DFE receiver with far-end crosstalk cancellation","author":"nazari","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2197233"},{"key":"ref4","first-page":"112","article-title":"A 3.2 Gb\/s 8 b single-ended integrating DFE RX for 2-drop DRAM interface with internal reference voltage and digital calibration","author":"chi","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","first-page":"193","article-title":"40 nm 7 Gb\/s\/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface","author":"bae","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320971"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864113"},{"key":"ref8","article-title":"A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel","author":"bae","year":"2010","journal-title":"Proc IEEE Custom Integrated Circuits Conf (CICC)"},{"key":"ref7","first-page":"498","article-title":"A 40 nm 2 Gb 7 Gb\/s\/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW","author":"bae","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2075410"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672166"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6583962\/06548094.pdf?arnumber=6548094","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:42Z","timestamp":1638217722000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548094\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":18,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2264618","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,9]]}}}