{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,6]],"date-time":"2026-06-06T17:14:09Z","timestamp":1780766049739,"version":"3.54.1"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/jssc.2013.2272340","type":"journal-article","created":{"date-parts":[[2013,7,24]],"date-time":"2013-07-24T22:51:52Z","timestamp":1374706312000},"page":"3134-3145","source":"Crossref","is-referenced-by-count":60,"title":["digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture"],"prefix":"10.1109","volume":"48","author":[{"given":"Roberto","family":"Nonis","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Werner","family":"Grollitsch","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thomas","family":"Santa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dmytro","family":"Cherniak","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nicola","family":"Da Dalt","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063630"},{"key":"ref12","first-page":"342","article-title":"A 0.27 mm2, 13.5 dBm, 2.4 GHz all-digital polar transmitter with 34%-efficiency class-D DPA in 40 nm CMOS","author":"lai","year":"2013","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref13","author":"da dalt","year":"2007","journal-title":"Theory and Implementation of Digital Bang-bang Frequency Synthesizers for High Speed Serial Data Communications"},{"key":"ref14","first-page":"356","article-title":"A 2.4 psrms-jitter digital PLL with multi-output bang-bang phase detector and phase-interpolator-based fractional-N divider","author":"nonis","year":"2013","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref4","first-page":"342","article-title":"A 20 Mb\/s phase modulator based on a 3.6 GHz digital PLL with <formula formulatype=\"inline\"><tex Notation=\"TeX\">$-36$<\/tex> <\/formula> EVM at 5 mW power","author":"marzin","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref6","first-page":"240","article-title":"A 0.004 mm2 250 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>W <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Sigma -\\Delta$<\/tex><\/formula> TDC with time-difference accumulator and a 0.012 mm2 2.5 mW bang-bang digital PLL Using PRNG for low-power SoC applications","author":"hong","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","first-page":"246","article-title":"A TDC-less ADPLL with 200-to-3200 MHz range and 3 mW power dissipation for mobile SoC clocking in 22 nm CMOS","author":"august","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2199530"},{"key":"ref7","first-page":"464","article-title":"A 13b 315 fsrms 2 mW 500 MS\/s 1 MHz bandwidth highly digital time-to-digital converter using switched ring oscillators","author":"elshazly","year":"2012","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref2","first-page":"356","article-title":"A 1.4 ps-rms period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS","author":"grollitsch","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref9","first-page":"480","article-title":"A 1.7 mW 11 b 1-1-1 MASH <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> time-to-digital converter","author":"cao","year":"2011","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6671390\/06568013.pdf?arnumber=6568013","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:43Z","timestamp":1638217723000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6568013\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":14,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2272340","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,12]]}}}