{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,26]],"date-time":"2026-07-26T10:03:38Z","timestamp":1785060218927,"version":"3.55.0"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/jssc.2013.2273836","type":"journal-article","created":{"date-parts":[[2013,8,7]],"date-time":"2013-08-07T18:02:33Z","timestamp":1375898553000},"page":"2419-2429","source":"Crossref","is-referenced-by-count":50,"title":["A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration"],"prefix":"10.1109","volume":"48","author":[{"given":"Salvatore","family":"Levantino","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"Marzin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carlo","family":"Samori","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022916"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022304"},{"key":"ref31","first-page":"328","article-title":"A 2.5 Gb\/s multi-rate 0.25 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS CDR utilizing a hybrid analog\/digital loop filter","author":"perrott","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.840089"},{"key":"ref35","first-page":"50","article-title":"Suppression of flicker noise upconversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz bandwidth","author":"levantino","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672113"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2209809"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"472","DOI":"10.1109\/TCSII.2011.2158752","article-title":"A 2.4-GHz extended-range type-I <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Sigma \\Delta$<\/tex><\/formula> fractional-N synthesizer with 1.8-MHz loop bandwidth and <formula formulatype=\"inline\"> <tex Notation=\"TeX\">${-}$<\/tex><\/formula>110-dBc\/Hz phase noise","volume":"58","author":"shekhar","year":"2011","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2104270"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/26.506392"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2012.6242258"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001873"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076570"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"497","DOI":"10.1109\/JSSC.2007.914325","article-title":"<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> PLL transmitter with a loop-bandwidth calibration system","volume":"43","author":"akamine","year":"2008","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"966","DOI":"10.1109\/JSSC.2006.870894","article-title":"A 1-MHz bandwidth 3.6-GHz 0.18-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS fractional-N synthesizer utilizing a hybrid PFD\/DAC structure for reduced broadband phase noise","volume":"41","author":"meninger","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831598"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"ref29","author":"walker","year":"2003","journal-title":"Phase Locking in High-Performance Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922721"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"768","DOI":"10.1109\/JSSC.2010.2040232","article-title":"A fractional-N PLL for multiband (0.8?6 GHz) communications using binary-weighted D\/A differentiator and offset-frequency <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Delta$<\/tex><\/formula>-<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Sigma$<\/tex><\/formula> modulator","volume":"45","author":"jian","year":"2010","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"3244","DOI":"10.1109\/JSSC.2009.2032713","article-title":"A 1 MHz bandwidth, 6 GHz 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS type-I <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> fractional-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$N$<\/tex><\/formula> synthesizer for WIMAX applications","volume":"44","author":"hedayati","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"2426","DOI":"10.1109\/JSSC.2009.2021086","article-title":"A FIR-embedded noise filtering method for <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> fractional-N PLL clock generators","volume":"44","author":"yu","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2161500"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032585"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2039832"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511541131"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883197"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6605547\/06576220.pdf?arnumber=6576220","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:43Z","timestamp":1638217723000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6576220\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":35,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2273836","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10]]}}}