{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T18:49:34Z","timestamp":1769280574692,"version":"3.49.0"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2013,11,1]],"date-time":"2013-11-01T00:00:00Z","timestamp":1383264000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2013,11]]},"DOI":"10.1109\/jssc.2013.2274852","type":"journal-article","created":{"date-parts":[[2013,10,21]],"date-time":"2013-10-21T20:08:07Z","timestamp":1382386087000},"page":"2637-2648","source":"Crossref","is-referenced-by-count":47,"title":["A 64-fJ\/Conv.-Step Continuous-Time &lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;$\\Sigma \\Delta$&lt;\/tex&gt;&lt;\/formula&gt; Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital &lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;$\\Delta \\Sigma$&lt;\/tex&gt;&lt;\/formula&gt; Truncator"],"prefix":"10.1109","volume":"48","author":[{"given":"Hung-Chieh","family":"Tsai","sequence":"first","affiliation":[]},{"given":"Chi-Lun","family":"Lo","sequence":"additional","affiliation":[]},{"given":"Chen-Yen","family":"Ho","sequence":"additional","affiliation":[]},{"given":"Yu-Hsin","family":"Lin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022298"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.890296"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"2669","DOI":"10.1109\/JSSC.2006.884231","article-title":"A 6-bit 600-MS\/s 5.3-mW asynchronous ADC in 0.13-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>m CMOS","volume":"41","author":"chen","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126390"},{"key":"ref16","author":"murmann","year":"2012","journal-title":"?ADC Performance Survey 1997-2012 ?"},{"key":"ref17","article-title":"A 95 dB SNDR audio <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> modulator in 65 nm CMOS","author":"liu","year":"2011","journal-title":"Proc IEEE CICC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047423"},{"key":"ref19","first-page":"241","article-title":"A 1.2 V 64 fJ\/conversion-step continuous-time <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Sigma \\Delta$<\/tex><\/formula> modulator using asynchronous SAR quantizer and digital <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> truncator","author":"tsai","year":"2012","journal-title":"Proc IEEE A-SSCC"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856282"},{"key":"ref27","author":"schreier","year":"2005","journal-title":"Understanding Delta-Sigma Data Converters"},{"key":"ref3","first-page":"414","article-title":"A 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS 0.1?20 MHz bandwidth 86?70 dB DR multi-mode DT <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> ADC for IMT-advanced","author":"christen","year":"2010","journal-title":"Proc IEEE ESSCIRC"},{"key":"ref6","first-page":"42","article-title":"A 2.8 mW <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex> <\/formula> ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator","author":"gealow","year":"2011","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref5","first-page":"244","article-title":"A 5th-order CT\/DT multi-mode <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> modulator","author":"putter","year":"2007","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","article-title":"A 69.8 dB SNDR 3rd-order continuous time delta-sigma modulator with a ultimate low power tuning system for a worldwide digital TV-receiver","author":"matsukawa","year":"2010","journal-title":"Proc IEEE CICC"},{"key":"ref7","first-page":"160","article-title":"A 10 MHz BW 50 fJ\/conv. continuous time <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> modulator with high-order single Opamp integrator using optimization-based design method","author":"matsukawa","year":"2012","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref2","first-page":"153","article-title":"A 2.8-to-8.5 mW GSM\/bluetooth\/UMTS\/DVB-H\/WLAN fully reconfigurable CT <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex> <\/formula> with 200 kHz to 20 MHz BW for 4 G radios in 90 nm digital CMOS","author":"ke","year":"2010","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2167369"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2046230"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020525"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032703"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"2069","DOI":"10.1109\/JSSC.2003.819165","article-title":"A triple-mode continuous-time <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Sigma \\Delta$<\/tex><\/formula> modulator with switched-capacitor feedback DAC for a GSM-EDGE\/CDMA2000\/UMTS receiver","volume":"38","author":"van veldhoven","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref24","first-page":"386","article-title":"A 10 b 100 MS\/s 1.13 mW SAR ADC with binary-scaled error compensation","author":"liu","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref23","first-page":"172","article-title":"A 1.2 V 2 MHz BW 0.084 mm2 CT <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex> <\/formula> ADC with <formula formulatype=\"inline\"><tex Notation=\"TeX\">${-}$<\/tex> <\/formula>97.7 dBc THD and 80 dB DR using low-latency DEM","author":"huang","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.814432"},{"key":"ref25","first-page":"244","article-title":"A 1.9 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>W 4.4 fJ\/conversion-step 10 b 1 MS\/s charge-redistribution ADC","author":"van elzakker","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6642065\/06578611.pdf?arnumber=6578611","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:44Z","timestamp":1638217724000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6578611\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,11]]},"references-count":27,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2274852","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,11]]}}}