{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,22]],"date-time":"2025-05-22T06:05:51Z","timestamp":1747893951554},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/jssc.2013.2280308","type":"journal-article","created":{"date-parts":[[2013,9,25]],"date-time":"2013-09-25T18:25:39Z","timestamp":1380133539000},"page":"127-139","source":"Crossref","is-referenced-by-count":19,"title":["A 6.4-Gb\/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems"],"prefix":"10.1109","volume":"49","author":[{"given":"Michael","family":"Bucher","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravi T.","family":"Kollipara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruce","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liji","family":"Gopalakrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kashinath","family":"Prabhu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pravin Kumar","family":"Venkatesan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kambiz","family":"Kaviani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Barry","family":"Daly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B. William F.","family":"Stonecypher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Dettloff","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Teva","family":"Stone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fred","family":"Heaton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Madden","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanath","family":"Bangalore","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John C.","family":"Eble","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nhat M.","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Luo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1362","article-title":"Characterization of a low-power 6.4 Gb\/s DDR DIMM memory interface system","author":"kollipara","year":"2013","journal-title":"Proc IEEE Electron Compon Technol Conf"},{"key":"ref3","first-page":"417","article-title":"Improved power and data efficiency with threaded modules","author":"ware","year":"2007","journal-title":"Proc Int Conf Comput Design"},{"key":"ref10","first-page":"278","article-title":"A 60 nm 6 Gb\/s\/pin GDDR5 graphics DRAM with multifaceted clocking and ISI\/SSN-reduction techniques","author":"bae","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825259"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185370"},{"key":"ref5","year":"2012","journal-title":"DDR4 SDRAM JEDEC Solid State Technology Association"},{"key":"ref12","first-page":"82","article-title":"A 5.6 Gb\/s 2.4 mW\/Gb\/s bidirectional link with 8 ns power-on","author":"zerbe","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","first-page":"136","article-title":"Single-ended transceiver design techniques for 5.33 Gb\/s graphics applications","author":"partovi","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.21"},{"key":"ref9","first-page":"132","article-title":"A 0.4 mW\/Gb\/s 16 Gb\/s near-ground receiver front-end with replica transconductance termination calibration","author":"kaviani","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2009.5338468"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6690141\/06609131.pdf?arnumber=6609131","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:45Z","timestamp":1638217725000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6609131\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2280308","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}