{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T03:34:46Z","timestamp":1761708886904},"reference-count":12,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/jssc.2013.2280312","type":"journal-article","created":{"date-parts":[[2013,9,20]],"date-time":"2013-09-20T18:03:35Z","timestamp":1379700215000},"page":"118-126","source":"Crossref","is-referenced-by-count":13,"title":["A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit"],"prefix":"10.1109","volume":"49","author":[{"given":"Fumihiko","family":"Tachibana","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osamu","family":"Hirabayashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasuhisa","family":"Takeyama","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miyako","family":"Shizuno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Atsushi","family":"Kawasumi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keiichi","family":"Kushida","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Azuma","family":"Suzuki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuke","family":"Niki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shinichi","family":"Sasaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomoaki","family":"Yabe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yasuo","family":"Unekawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179 <ref_formula><tex Notation=\"TeX\">$\\mu\\hbox{m}^{2}$<\/tex><\/ref_formula> cell in 40 nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"210","article-title":"A 0.6 V 45 nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs","author":"chen","year":"2008","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838014"},{"key":"ref6","first-page":"382","article-title":"A single-power supply 0.7 V 1 GHz 45 nm SRAM with an asymmetrical, unit b-ratio memory cell","author":"kawasumi","year":"2008","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123627"},{"key":"ref12","first-page":"1","article-title":"0.5-V input digital LDO with 98.7% current efficiency and 2.7-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>A quiescent current in 65 nm CMOS","author":"okuma","year":"2010","journal-title":"Proc CICC"},{"key":"ref8","first-page":"348","article-title":"A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149 um2 cell in 32 nm high-k metal-gate CMOS","author":"fujimura","year":"2010","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586011"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342728"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2011.6123628"},{"key":"ref1","first-page":"2572","article-title":"A 4.2 GHz 0.3 mm2 256 kb dual-Vcc SRAM building block in 65 nm CMOS","author":"khellah","year":"2006","journal-title":"ISSCC Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6690141\/06605611.pdf?arnumber=6605611","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:45Z","timestamp":1638217725000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6605611\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":12,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2280312","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}