{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,29]],"date-time":"2026-05-29T10:25:53Z","timestamp":1780050353620,"version":"3.53.1"},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/jssc.2013.2284367","type":"journal-article","created":{"date-parts":[[2013,10,18]],"date-time":"2013-10-18T18:06:29Z","timestamp":1382119589000},"page":"95-106","source":"Crossref","is-referenced-by-count":55,"title":["An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at &lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;${\\rm VDD}=$&lt;\/tex&gt;&lt;\/formula&gt; 0 V Achieving Zero Leakage With &lt;formula formulatype=\"inline\"&gt;&lt;tex Notation=\"TeX\"&gt;${&amp;lt;}$&lt;\/tex&gt; &lt;\/formula&gt;400-ns Wakeup Time for ULP Applications"],"prefix":"10.1109","volume":"49","author":[{"given":"Sudhanshu","family":"Khanna","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Steven C.","family":"Bartling","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Clinton","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Scott","family":"Summerfelt","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John A.","family":"Rodriguez","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hugh P.","family":"McAdams","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249428"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2002.1175897"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCDG.2012.6360000"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICGCS.2010.5542984"},{"key":"ref8","first-page":"192","article-title":"A 3.4 pJ FeRAM-enabled D flip-flop in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS for nonvolatile processing in digital systems","author":"qazi","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341281"},{"key":"ref2","first-page":"202","article-title":"A MCU platform with embedded FRAM achieving 350 nA current consumption in real-time clock mode with full state retention and 6.5 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>s system wakeup time","author":"baumann","year":"2013","journal-title":"Proc IEEE VLSI Symp"},{"key":"ref9","first-page":"432","article-title":"An 8 MHz 75 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>A\/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at <formula formulatype=\"inline\"> <tex Notation=\"TeX\">${\\rm VDD}=0$<\/tex><\/formula> V with <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$&#60;400$<\/tex><\/formula> ns wakeup and sleep transitions","author":"bartling","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref1","first-page":"334, 336","article-title":"An 82 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>A\/MHz microcontroller with embedded FeRAM for energy-harvesting applications","author":"zwerg","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6690141\/06637100.pdf?arnumber=6637100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:28:46Z","timestamp":1638217726000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6637100\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":9,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2013.2284367","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}