{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T18:48:41Z","timestamp":1777488521185,"version":"3.51.4"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/jssc.2014.2299273","type":"journal-article","created":{"date-parts":[[2014,1,31]],"date-time":"2014-01-31T17:42:16Z","timestamp":1391190136000},"page":"1027-1035","source":"Crossref","is-referenced-by-count":40,"title":["A 28 GHz Hybrid PLL in 32 nm SOI CMOS"],"prefix":"10.1109","volume":"49","author":[{"given":"Mark","family":"Ferriss","sequence":"first","affiliation":[]},{"given":"Alexander","family":"Rylyakov","sequence":"additional","affiliation":[]},{"given":"Jose A.","family":"Tierno","sequence":"additional","affiliation":[]},{"given":"Herschel","family":"Ainspan","sequence":"additional","affiliation":[]},{"given":"Daniel J.","family":"Friedman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"98","article-title":"A 570 fs rms integrated-jitter ring-VCO-based 1.21 GHz PLL with hybrid loop","author":"sai","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239114"},{"key":"ref13","article-title":"A 12 GHz 210 fs 6 mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO","author":"ru","year":"2013","journal-title":"Symp VLSI Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/82.275664"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917500"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917405"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2221197"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884391"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2010109"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883197"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157259"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977324"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6777594\/06720214.pdf?arnumber=6720214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:29:23Z","timestamp":1642004963000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6720214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":13,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2299273","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}