{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T12:01:26Z","timestamp":1772798486459,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/jssc.2014.2316241","type":"journal-article","created":{"date-parts":[[2014,4,24]],"date-time":"2014-04-24T18:02:26Z","timestamp":1398362546000},"page":"1487-1498","source":"Crossref","is-referenced-by-count":44,"title":["0.77 fJ\/bit\/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance"],"prefix":"10.1109","volume":"49","author":[{"given":"Anh Tuan","family":"Do","sequence":"first","affiliation":[]},{"given":"Chun","family":"Yin","sequence":"additional","affiliation":[]},{"given":"Kavitha","family":"Velayudhan","sequence":"additional","affiliation":[]},{"given":"Zhao Chuan","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Kiat Seng","family":"Yeo","sequence":"additional","affiliation":[]},{"given":"Tony Tae-Hyoung","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"83","article-title":"A 128 <ref_formula><tex Notation=\"TeX\">$\\times$<\/tex><\/ref_formula> 128b high-speed wide-and match-line content addressable memory in 32 nm CMOS","author":"agarwal","year":"2011","journal-title":"Proc ESSCIRC 2001 Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.839913"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.924858"},{"key":"ref13","first-page":"926","article-title":"Power modeling and low-power design of content addressable memories","volume":"4","author":"hsiao","year":"2001","journal-title":"IEEE Int Symp Circuits Systems ISCAS 95"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1485","DOI":"10.1109\/TCSI.2008.916624","article-title":"Low-power ternary content-addressable memory design using a segmented match line","volume":"55","author":"sanghyeon","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249424"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001932"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243817"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"507","DOI":"10.1109\/JSSC.2010.2082270","article-title":"A 65 nm 0.165 fJ\/Bit\/search 256<ref_formula> <tex Notation=\"TeX\">$\\times$<\/tex><\/ref_formula>144 TCAM macro design for IPv6 lookup tables","volume":"46","author":"po-tsang","year":"2011","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320819"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2042826"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274888"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915514"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838016"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.72"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2009.2030188"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2012.2220566"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.858696"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818139"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000247"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1165573.1165605"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243781"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6164998"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2037995"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6841653\/06805234.pdf?arnumber=6805234","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:55:58Z","timestamp":1642006558000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6805234\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":25,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2316241","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}