{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:55:47Z","timestamp":1774720547813,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/jssc.2014.2322853","type":"journal-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T20:07:14Z","timestamp":1401480434000},"page":"1366-1382","source":"Crossref","is-referenced-by-count":47,"title":["A 12 bit 200 MS\/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration"],"prefix":"10.1109","volume":"49","author":[{"given":"Soon-Kyun","family":"Shin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacques C.","family":"Rudell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Denis C.","family":"Daly","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos E.","family":"Munoz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dong-Young","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kush","family":"Gulati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hae-Seung","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew Z.","family":"Straayer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2024809"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586015"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977358"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006309"},{"key":"ref37","first-page":"268c","article-title":"A 2.1 mW 11 b 410 MS\/s dynamic pipelined SAR ADC with background calibration in 28 nm digital CMOS","author":"verbruggen","year":"2013","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724689"},{"key":"ref35","first-page":"98c","article-title":"A 12-bit, 200-MS\/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end","author":"dolev","year":"2013","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref34","first-page":"292","article-title":"A 16 b 250 MS\/s IF-sampling pipelined A\/D converter with background calibration","author":"ali","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref10","first-page":"460","article-title":"A zero-crossing-based 8 b 200 MS\/s pipelined ADC","author":"brooks","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref11","first-page":"218","article-title":"A fully differential zero-crossing-based 1.2 V 10 b 26 MS\/s pipelined ADC in 65 nm CMOS","author":"shin","year":"2008","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref12","first-page":"166","article-title":"A 12 b 50 MS\/s fully differential zero-crossing based ADC without CMFB","author":"brooks","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref13","first-page":"237","article-title":"A zero-crossing based 12 b 100 MS\/s pipelined ADC with decision boundary gap estimation calibration","author":"chu","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref14","author":"guyton","year":"2010","journal-title":"A Low-voltage Zero-crossing-based Delta-sigma Analog-todigital Converter"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2191184"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055327"},{"key":"ref17","first-page":"1","article-title":"A 630 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>W zero-crossing-based <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\Delta \\Sigma$<\/tex><\/formula> ADC using switched-resistor current sources in 45 nm CMOS","author":"musah","year":"2009","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2010.5716604"},{"key":"ref19","first-page":"1","article-title":"A 12 b 200 MS\/s frequency scalable zero-crossing based pipelined ADC in 55 nm CMOS","author":"shin","year":"2012","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref28","first-page":"832","article-title":"A 14 b 100 MS\/s digitally self-calibrated pipelined ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>m CMOS","author":"bogner","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref4","first-page":"239","article-title":"A 12 b 50 MS\/s 3.5 mW SAR assisted 2-stage pipeline ADC","author":"lee","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref27","author":"murmann","year":"0","journal-title":"?ADC Performance Survey 1997?2013 ?"},{"key":"ref3","first-page":"86","article-title":"A 16 b 125 MS\/s 385 mW 78.7 dB SNR CMOS pipeline ADC","author":"devarajan","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234320"},{"key":"ref29","first-page":"74","article-title":"A 1.2 V 250 mW 14 b 100 MS\/s digitally calibrated pipeline ADC in 90 nm CMOS","author":"van de vel","year":"2008","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref5","first-page":"186","article-title":"A 16 b 80 MS\/s 100 mw 77.6 dB SNR CMOS pipeline ADC","author":"brunsilius","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","first-page":"1","article-title":"A 10 b 320 MS\/s self-calibrated pipelined ADC","author":"chen","year":"2010","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.1004571"},{"key":"ref2","first-page":"220","article-title":"A 12 b 50 MS\/s 10.2 mA 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS Nyquist ADC with a fully differential class-AB switched OP-AMP","author":"choi","year":"2008","journal-title":"Proc IEEE Symp VLSI Circ Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696121"},{"key":"ref1","first-page":"256","article-title":"A 1.2 V 220 MS\/s 10 b pipeline ADC implemented in 0.13 um digital CMOS","author":"hernes","year":"2004","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649085"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"315","DOI":"10.1109\/JPROC.2009.2032570","article-title":"Zero-crossing-based ultra-low-power A\/D converters","volume":"98","author":"lee","year":"2010","journal-title":"Proc IEEE"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217865"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2073190"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006312"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"},{"key":"ref25","first-page":"566","article-title":"A 0.19 pJ\/Conversion-step 2.5 mW 1.25 GS\/s 4 b ADC in a 90 nm Digital CMOS Process","author":"vad der plas","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6822663\/06822690.pdf?arnumber=6822690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:56:15Z","timestamp":1642006575000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6822690"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":37,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2322853","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,6]]}}}