{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T19:58:21Z","timestamp":1769284701747,"version":"3.49.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/jssc.2014.2357428","type":"journal-article","created":{"date-parts":[[2014,10,16]],"date-time":"2014-10-16T19:03:49Z","timestamp":1413486229000},"page":"24-34","source":"Crossref","is-referenced-by-count":33,"title":["Steamroller Module and Adaptive Clocking System in 28 nm CMOS"],"prefix":"10.1109","volume":"50","author":[{"given":"Kathryn","family":"Wilcox","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Cole","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Harry R.","family":"Fair III","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Gillespie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aaron","family":"Grenat","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carson","family":"Henrion","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravi","family":"Jotwani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen","family":"Kosonocky","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benjamin","family":"Munger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Samuel","family":"Naffziger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert S.","family":"Orefice","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjay","family":"Pant","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donald A.","family":"Priore","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ravinder","family":"Rachala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonathan","family":"White","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"456","article-title":"A 4.0 GHz 291 Mb voltage-scalable SRAM design in a 32 nm high-k metal-gate CMOS technology with integrated power management","author":"wang","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2012.6263922"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/APEC.2004.1295820"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014023"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859879"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090651"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.29"},{"key":"ref2","first-page":"78","article-title":"Design solutions for the Bulldozer 32 nm SOI 2-Core processor module in an 8-Core","author":"fischer","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.25"},{"key":"ref1","first-page":"104","article-title":"Steamroller: An x86?64 core implemented in 28 nm bulk CMOS","author":"gillespie","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6998099\/06926864.pdf?arnumber=6926864","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:27:49Z","timestamp":1642004869000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6926864\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":10,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2357428","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}