{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,6]],"date-time":"2026-06-06T17:13:58Z","timestamp":1780766038956,"version":"3.54.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/jssc.2014.2357432","type":"journal-article","created":{"date-parts":[[2014,10,21]],"date-time":"2014-10-21T18:54:07Z","timestamp":1413917647000},"page":"258-269","source":"Crossref","is-referenced-by-count":64,"title":["A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters"],"prefix":"10.1109","volume":"50","author":[{"given":"Christophe","family":"Erdmann","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Donnacha","family":"Lowney","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Adrian","family":"Lynam","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aidan","family":"Keady","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"John","family":"McGrath","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Edward","family":"Cullen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daire","family":"Breathnach","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Denis","family":"Keane","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Patrick","family":"Lynch","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marites","family":"De La Torre","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ronnie","family":"De La Torre","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peng","family":"Lim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Anthony","family":"Collins","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Brendan","family":"Farley","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Liam","family":"Madden","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-6579-3"},{"key":"ref11","author":"quinn","year":"2011","journal-title":"Smart and Flexible Digital-to-Analog Converters"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.808896"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052639"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/17\/12\/308"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/81.915383"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032624"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2011.6138617"},{"key":"ref4","first-page":"1601","article-title":"Through Silicon Via (TSV) design considering technology challenges for very high-speed signal transmission","volume":"2","author":"kim","year":"2011","journal-title":"Proc DesignCon"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2012.6343325"},{"key":"ref6","first-page":"540","article-title":"55-mW 1.2 V 12-bit 100-MSPS pipeline ADCs for wireless receivers","author":"ito","year":"2006","journal-title":"Proc ESSCIRC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185169"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.836230"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.847519"},{"key":"ref2","first-page":"120","article-title":"A heterogeneous 3D-IC consisting of two 28 nm FPGA die and 32 reconfigurable high-performance data converters","author":"erdmann","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"116","article-title":"Memory and system architecture for 400 Gb\/s networking and beyond","author":"maheshwari","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","author":"doris","year":"2006","journal-title":"Wide-Bandwidth High Dynamic Range D\/A Converters"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6998099\/06932508.pdf?arnumber=6932508","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:27:49Z","timestamp":1642004869000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6932508\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":18,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2357432","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}