{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T04:00:01Z","timestamp":1769918401091,"version":"3.49.0"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/jssc.2014.2360379","type":"journal-article","created":{"date-parts":[[2014,10,14]],"date-time":"2014-10-14T18:42:48Z","timestamp":1413312168000},"page":"191-203","source":"Crossref","is-referenced-by-count":88,"title":["A 1.2 V 8 Gb 8-Channel 128 GB\/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I\/O Test Circuits"],"prefix":"10.1109","volume":"50","author":[{"given":"Dong Uk","family":"Lee","sequence":"first","affiliation":[]},{"given":"Kyung Whan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Kwan Weon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Kang Seol","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Sang Jin","family":"Byeon","sequence":"additional","affiliation":[]},{"given":"Jae Hwan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jin Hee","family":"Cho","sequence":"additional","affiliation":[]},{"given":"Jaejin","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jun Hyun","family":"Chun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","year":"2013","journal-title":"JEDEC Standard High Bandwidth Memory (HBM) DRAM Specification"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085991"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004523"},{"key":"ref13","year":"2012","journal-title":"JEDEC Standard LPDDR3 SDRAM Specification"},{"key":"ref14","first-page":"44","article-title":"A 1.2 V 30 nm 1.6 Gb\/s\/pin 4 Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme","author":"bae","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908002"},{"key":"ref16","first-page":"40","article-title":"A 1.2 V 38 nm 2.4 Gb\/s\/pin 2 Gb DDR4 SDRAM with bank group and $\\,\\times 4$<\/tex><\/formula> half-page architecture","author":"koo","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487803"},{"key":"ref18","first-page":"142","article-title":"A compact low-power 3D I\/O in 45 nm CMOS","author":"liu","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523166"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164731"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref6","first-page":"116","article-title":"Memory and system architecture for 400 Gb\/s networking and beyond","author":"maheshwari","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2012.6343325"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2013.6575766"},{"key":"ref7","first-page":"16c","article-title":"An extra low-power 1 Tbit\/s bandwidth PLL\/DLL-less eDRAM PHY using 0.3 V low-swing IO for 2.5D CoWoS application","author":"lin","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"key":"ref9","first-page":"432","article-title":"A 1.2 V 8 Gb 8-channel 128 GB\/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I\/O test methods using 29 nm process and TSV","author":"lee","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref1","first-page":"2","article-title":"System scaling and collaborative open innovation","author":"sun","year":"2013","journal-title":"Symp VLSI Technol Dig Tech Papers"},{"key":"ref20","first-page":"735","article-title":"Use of MISRs for compression and diagnostics","author":"keller","year":"2005","journal-title":"Proc Int Test Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2246235"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011042"},{"key":"ref24","first-page":"1031","article-title":"TSV manufacturing yield and hidden costs for 3-D IC integration","author":"lau","year":"2011","journal-title":"Proc Electron Compon Technol Conf"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908004"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280778"},{"key":"ref25","first-page":"23","article-title":"AC IO loopback design for high speed $\\mu $<\/tex> <\/formula> processor IO test","author":"provost","year":"2004","journal-title":"Proc Int Test Conf"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6998099\/06923498.pdf?arnumber=6923498","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:27:49Z","timestamp":1642004869000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6923498\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":26,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2360379","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}