{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,3]],"date-time":"2026-03-03T23:38:44Z","timestamp":1772581124149,"version":"3.50.1"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2014,12,1]],"date-time":"2014-12-01T00:00:00Z","timestamp":1417392000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/jssc.2014.2361774","type":"journal-article","created":{"date-parts":[[2014,10,23]],"date-time":"2014-10-23T21:30:40Z","timestamp":1414099840000},"page":"2835-2845","source":"Crossref","is-referenced-by-count":91,"title":["A 1.5 mW 68 dB SNDR 80 Ms\/s 2&lt;formula formulatype=\"inline\"&gt; &lt;tex Notation=\"TeX\"&gt;$\\times$&lt;\/tex&gt;&lt;\/formula&gt; Interleaved Pipelined SAR ADC in 28 nm CMOS"],"prefix":"10.1109","volume":"49","author":[{"given":"Frank","family":"van der Goes","sequence":"first","affiliation":[]},{"given":"Christopher M.","family":"Ward","sequence":"additional","affiliation":[]},{"given":"Santosh","family":"Astgimath","sequence":"additional","affiliation":[]},{"given":"Han","family":"Yan","sequence":"additional","affiliation":[]},{"given":"Jeff","family":"Riley","sequence":"additional","affiliation":[]},{"given":"Zeng","family":"Zeng","sequence":"additional","affiliation":[]},{"given":"Jan","family":"Mulder","sequence":"additional","affiliation":[]},{"given":"Sijia","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Klaas","family":"Bult","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487731"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523145"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2002547"},{"key":"ref13","first-page":"472","article-title":"A 14 b 80 MS\/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS","author":"kapusta","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464555"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2244317"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937491"},{"key":"ref17","author":"astgimath","year":"2012","journal-title":"?A low-noise low-power dynamic amplifier with common mode detect and a low-power low-noise comparator for pipelined SAR-ADC ?"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917991"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref4","author":"murmann","year":"0","journal-title":"ADC Performance Survey 1997?2013"},{"key":"ref3","first-page":"92c","article-title":"A 5.4 GS\/s 12 b 500 mW pipeline ADC in 28 nm CMOS","author":"wu","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref6","first-page":"239","article-title":"A 12 b 50 MS\/s 3.5 mW SAR assisted 2-stage pipeline ADC","author":"lee","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917427"},{"key":"ref8","first-page":"466","article-title":"A 1.7 mW 11 b 250 MS\/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS","author":"verbruggen","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","first-page":"1","article-title":"A 9.15 mW 0.22 mm2 10 b 204 MS\/s pipelined SAR ADC in 65 nm CMOS","author":"jeon","year":"2010","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref2","first-page":"292","article-title":"A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65 nm CMOS","author":"janssen","year":"2011","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/NTC.1992.267870"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487730"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"2669","DOI":"10.1109\/JSSC.2006.884231","article-title":"A 6-bit 600-MS\/s 5.3 mW asynchronous ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu\\hbox{m}$<\/tex> <\/formula> CMOS","volume":"41","author":"chen","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000501"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6963535\/06935025.pdf?arnumber=6935025","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:00:55Z","timestamp":1642003255000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6935025\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":21,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2361774","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,12]]}}}