{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,14]],"date-time":"2026-01-14T04:16:39Z","timestamp":1768364199673,"version":"3.49.0"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,1]]},"DOI":"10.1109\/jssc.2014.2368933","type":"journal-article","created":{"date-parts":[[2014,12,4]],"date-time":"2014-12-04T15:19:50Z","timestamp":1417706390000},"page":"35-48","source":"Crossref","is-referenced-by-count":7,"title":["A 22 nm 15-Core Enterprise Xeon\u00ae Processor Family"],"prefix":"10.1109","volume":"50","author":[{"given":"Stefan","family":"Rusu","sequence":"first","affiliation":[{"name":"Intel Corporation, Santa Clara, CA, USA"}]},{"given":"Harry","family":"Muljono","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"David","family":"Ayers","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Simon","family":"Tam","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Wei","family":"Chen","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Aaron","family":"Martin","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Shenggao","family":"Li","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Sujal","family":"Vora","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Raj","family":"Varada","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]},{"given":"Eddie","family":"Wang","sequence":"additional","affiliation":[{"name":"Intel Corporation, Santa Clara"}]}],"member":"263","reference":[{"key":"ref4","year":"2014","journal-title":"Intel Platform Roadmap"},{"key":"ref3","article-title":"A 22nm high performance and low power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors","author":"auth","year":"2012","journal-title":"VLSI Symp Dig"},{"key":"ref10","article-title":"Automated pseudo-flat design methodology for register arrays","author":"varada","year":"2009","journal-title":"Proc DAC"},{"key":"ref6","article-title":"A 45nm 8-core Enterprise Xeon\ufffd processor","author":"rusu","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref11","article-title":"Superblock: A method for synthesizing large high performance designs without hierarchy limits","author":"varada","year":"2010","journal-title":"Proc DAC"},{"key":"ref5","article-title":"A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon\ufffd processor","author":"chen","year":"2013","journal-title":"VLSI Symp Dig"},{"key":"ref8","article-title":"A 78mW 11.8Gb\/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS","author":"spagna","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","article-title":"Intel\ufffd Quickpath interconnect architectural features supporting scalable system architectures","author":"ziakas","year":"2010","journal-title":"15th IEEE Symposium on High-Performance Interconnects (HOTI)"},{"key":"ref2","article-title":"A 22nm IA multi-CPU and GPU system-on-chip","author":"damaraju","year":"2012","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746229"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757356"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/6998099\/06975254.pdf?arnumber=6975254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T20:59:12Z","timestamp":1768337952000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6975254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1]]},"references-count":11,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2368933","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1]]}}}