{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,4]],"date-time":"2024-07-04T10:39:14Z","timestamp":1720089554885},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2015,4,1]],"date-time":"2015-04-01T00:00:00Z","timestamp":1427846400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1109\/jssc.2014.2371136","type":"journal-article","created":{"date-parts":[[2014,12,11]],"date-time":"2014-12-11T19:46:11Z","timestamp":1418327171000},"page":"856-866","source":"Crossref","is-referenced-by-count":12,"title":["A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS"],"prefix":"10.1109","volume":"50","author":[{"given":"Chang-Hyeon","family":"Lee","sequence":"first","affiliation":[]},{"given":"Lindel","family":"Kabalican","sequence":"additional","affiliation":[]},{"given":"Yan","family":"Ge","sequence":"additional","affiliation":[]},{"given":"Hendra","family":"Kwantono","sequence":"additional","affiliation":[]},{"given":"Greg","family":"Unruh","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Chambers","sequence":"additional","affiliation":[]},{"given":"Ichiro","family":"Fujimori","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SiRF.2012.6160144"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.953473"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2004.1346498"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780807"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912552"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658471"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.972142"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.658619"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.4682"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852732"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273836"},{"key":"ref4","first-page":"1705","article-title":"Switched resonators and their applications in a dual-band monolithic CMOS LC-tuned VCO","volume":"54","author":"yim","year":"2006","journal-title":"IEEE Trans Microw Theory Tech"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005704"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.814440"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2190185"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2209809"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011041"},{"key":"ref8","article-title":"A 2.7 GHz to 7 GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28 nm CMOS","author":"lee","year":"2014","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560320"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842851"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.668989"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2014.2302331"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.760384"},{"key":"ref22","article-title":"A 0.026 mm2 5.3 mW 32-to-2000 MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter","author":"jang","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","article-title":"A digitally stabilized type-III PLL using ring VCO with 1.01 ps_rms integrated jitter in 65 nm CMOS","author":"sai","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref23","article-title":"A low-spur fractional-N digital PLL for 802.11a\/b\/g\/n\/ac with 0.19 psrms jitter","author":"yao","year":"2011","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063630"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217856"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7066864\/06982234.pdf?arnumber=6982234","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:30:15Z","timestamp":1642005015000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6982234\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4]]},"references-count":29,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2371136","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,4]]}}}