{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T14:21:30Z","timestamp":1773843690022,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/jssc.2014.2387946","type":"journal-article","created":{"date-parts":[[2015,1,23]],"date-time":"2015-01-23T21:50:23Z","timestamp":1422049823000},"page":"704-713","source":"Crossref","is-referenced-by-count":64,"title":["An Interleaved Full Nyquist High-Speed DAC Technique"],"prefix":"10.1109","volume":"50","author":[{"given":"Erik","family":"Olieman","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anne-Johan","family":"Annema","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bram","family":"Nauta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937409"},{"key":"ref11","first-page":"390","article-title":"A 14b 4.6 GS\/s RF DAC in 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>m CMOS for cable head-end systems","author":"mcmahill","year":"2014","journal-title":"2014 IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","first-page":"206","article-title":"A 110 mW, 0.04 mm<formula formulatype=\"inline\"><tex Notation=\"TeX\">$^2$<\/tex><\/formula>, 11 GS\/s 9-bit interleaved DAC in 28 nm FDSOI with <formula formulatype=\"inline\"><tex Notation=\"TeX\">${&#x003E;}$<\/tex><\/formula>50 dB SFDR across Nyquist","author":"olieman","year":"2014","journal-title":"2011 Symp VLSI Circuits (VLSIC) Dig"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803056"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"458","DOI":"10.1109\/ISSCC.2012.6177089","article-title":"A 14b 3\/6 GHz current-steering RF DAC in 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex><\/formula>m CMOS with 66 dB ACLR at 2.9 GHz","author":"engel","year":"2012","journal-title":"2012 IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","first-page":"360, 532","article-title":"A 3 V CMOS 400 mW 14b 1.4 GS\/s DAC for multi-carrier applications","author":"schafferer","year":"2004","journal-title":"2004 IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","first-page":"64","article-title":"A 3 GS\/s, 9b, 1.2 V single supply, pure binary DAC with <formula formulatype=\"inline\"><tex Notation=\"TeX\">${&#x003E;}$<\/tex> <\/formula>50 dB SFDR up to 1.5 GHz in 65 nm CMOS","author":"tual","year":"2011","journal-title":"2011 Symp VLSI Circuits (VLSIC) Dig"},{"key":"ref17","first-page":"262c","article-title":"A 13-bit 9 GS\/s RF DAC-based broadband transmitter in 28 nm CMOS","author":"xiao","year":"2013","journal-title":"VLSI Circuits (VLSIC) 2013 Symposium on"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746279"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2005.1522971"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2301769"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2013.6690987"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032624"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681842"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.829968"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.890297"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.808897"},{"key":"ref9","year":"1975","journal-title":"Antiglitch Digital to Analog Converter System"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7049386\/07019002.pdf?arnumber=7019002","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:45:40Z","timestamp":1642005940000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7019002\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":18,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2014.2387946","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3]]}}}