{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T10:50:21Z","timestamp":1775645421849,"version":"3.50.1"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/jssc.2015.2464684","type":"journal-article","created":{"date-parts":[[2015,9,4]],"date-time":"2015-09-04T18:54:32Z","timestamp":1441392872000},"page":"2922-2934","source":"Crossref","is-referenced-by-count":68,"title":["A 5 GS\/s 150 mW 10 b SHA-Less Pipelined\/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS"],"prefix":"10.1109","volume":"50","author":[{"given":"Massimo","family":"Brandolini","sequence":"first","affiliation":[]},{"given":"Young J.","family":"Shin","sequence":"additional","affiliation":[]},{"given":"Karthik","family":"Raviprakash","sequence":"additional","affiliation":[]},{"given":"Tao","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Rong","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Hemasundar Mohan","family":"Geddada","sequence":"additional","affiliation":[]},{"given":"Yen-Jen","family":"Ko","sequence":"additional","affiliation":[]},{"given":"Yen","family":"Ding","sequence":"additional","affiliation":[]},{"given":"Chun-Sheng","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Wei-Ta","family":"Shih","sequence":"additional","affiliation":[]},{"given":"Ming-Hung","family":"Hsieh","sequence":"additional","affiliation":[]},{"given":"Acer Wei-Te","family":"Chou","sequence":"additional","affiliation":[]},{"given":"Tianwei","family":"Li","sequence":"additional","affiliation":[]},{"given":"Ayaskant","family":"Shrivastava","sequence":"additional","affiliation":[]},{"given":"Dominique Yi-Chun","family":"Chen","sequence":"additional","affiliation":[]},{"given":"Bryan Juo-Jung","family":"Hung","sequence":"additional","affiliation":[]},{"given":"Giuseppe","family":"Cusmai","sequence":"additional","affiliation":[]},{"given":"Jiangfeng","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Mo Maggie","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Yuan","family":"Yao","sequence":"additional","affiliation":[]},{"given":"Greg","family":"Unruh","sequence":"additional","affiliation":[]},{"given":"Ardie","family":"Venes","sequence":"additional","affiliation":[]},{"given":"Hung Sen","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Chun-Ying","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252518"},{"key":"ref11","first-page":"124","article-title":"A 22-mW 7 b 1.3-GS\/s pipeline ADC with 1-bit\/stage folding converter architecture","author":"yamase","year":"2011","journal-title":"Symp VLSI Circuits (VLSI) Dig"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2151510"},{"key":"ref13","first-page":"202","article-title":"A 100 MS\/s 10.5 b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers","author":"lim","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","first-page":"468","article-title":"A 5 GS\/S 150 mW 10 b SHA-less pipelined\/SAR hybrid ADC in 28 nm CMOS","author":"brandolini","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","author":"murmann","year":"0","journal-title":"ADC Performance Survey 1997?2015"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361774"},{"key":"ref17","first-page":"1","article-title":"An 11.5-ENOB 100-MS\/s 8 mW dual-reference SAR ADC in 28 nm CMOS","author":"inerfield","year":"2014","journal-title":"Symp VLSI Circuits (VLSI) Dig"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693356"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2471-4"},{"key":"ref28","first-page":"192","article-title":"An 8.5 mW, 0.07 mm$^{2}$<\/tex><\/formula> ADPLL in 28 nm CMOS with sub-ps resolution TDC and $<$<\/tex><\/formula>230 fs RMS jitter","author":"shen","year":"2013","journal-title":"Symp VLSI Circuits Dig"},{"key":"ref4","first-page":"84","article-title":"A 2.8 GS\/s 44.6 mW TI ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS","author":"stepanovic","year":"2012","journal-title":"Symposium on VLSI Circuits (VLSIC)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2010.5784646"},{"key":"ref3","first-page":"386","article-title":"A 1.62 GS\/s TI SAR ADC with fully digital background mismatch compensation achieving interleaving spurs below 70 dBFS","author":"le dortz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","first-page":"470","article-title":"A 2.6 b\/cycle-architecture-based 10 b 1.7 GS\/s 15.4 mW 4$\\times$<\/tex> <\/formula>-time-interleaved SAR ADC with a multistep hardware-retirement technique","author":"hong","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"464","article-title":"A 21 fJ\/conv-step 9 ENOB 1.6 GS\/s 2$\\times$<\/tex><\/formula> time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45 nm CMOS","author":"sung","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"ref7","first-page":"92","article-title":"A 5.4 GS\/s 12 b 500 mW pipeline ADC in 28 nm CMOS","author":"wu","year":"2013","journal-title":"Symp VLSI Circuits (VLSI) Dig"},{"key":"ref2","first-page":"464","article-title":"An 11 b 3.6 GS\/s TI SAR ADC in 65 nm CMOS","author":"janssen","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"182","article-title":"A 12 b 1 GS\/s SiGe BiCMOS two-way time interleaved pipeline ADC","author":"payne","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/81.915383"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.875291"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892169"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.851387"},{"key":"ref24","first-page":"1","article-title":"A 0.45 mW 12 b 12.5 MS\/s SAR ADC with digital calibration","author":"li","year":"2014","journal-title":"Proc IEEE Custom Integrated Circuits Conf (CICC)"},{"key":"ref23","first-page":"460","article-title":"A 5.5 fJ\/conv-step 6.4 MS\/S 13 b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme","author":"ming","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.210039"},{"key":"ref25","first-page":"1","article-title":"A 12 b 160 MS\/s synchronous two-step SAR ADC achieving 20.7 fJ\/step FoM with opportunistic digital background calibration","author":"zhou","year":"2014","journal-title":"Symp VLSI Circuits (VLSI) Dig"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7336577\/07243368.pdf?arnumber=7243368","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:45:51Z","timestamp":1642005951000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7243368\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":28,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2464684","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}