{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,10]],"date-time":"2026-01-10T18:44:42Z","timestamp":1768070682690,"version":"3.49.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/jssc.2015.2472601","type":"journal-article","created":{"date-parts":[[2015,9,7]],"date-time":"2015-09-07T14:27:13Z","timestamp":1441636033000},"page":"2786-2795","source":"Crossref","is-referenced-by-count":29,"title":["Low ${\\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations"],"prefix":"10.1109","volume":"50","author":[{"given":"Meng-Fan","family":"Chang","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Jui-Jen","family":"Wu","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Tun-Fei","family":"Chien","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Yen-Chen","family":"Liu","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Ting-Chin","family":"Yang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Wen-Chao","family":"Shen","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Ya-Chin","family":"King","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Chrong Jung","family":"Lin","sequence":"additional","affiliation":[{"name":"National Tsing Hua University (NTHU), Hsinchu, Taiwan"}]},{"given":"Ku-Feng","family":"Lin","sequence":"additional","affiliation":[{"name":"ENVM, MSD\/DTP, Taiwan Semiconductor Manufacturing Company (TSMC), Ltd., Hsinchu, Taiwan"}]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[{"name":"ENVM, MSD\/DTP, Taiwan Semiconductor Manufacturing Company (TSMC), Ltd., Hsinchu, Taiwan"}]},{"given":"Jonathan","family":"Chang","sequence":"additional","affiliation":[{"name":"ENVM, MSD\/DTP, Taiwan Semiconductor Manufacturing Company (TSMC), Ltd., Hsinchu, Taiwan"}]}],"member":"263","reference":[{"key":"ref30","first-page":"350","article-title":"A 512 Kb 8T SRAM macro operating down to 0.57 V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45 nm SOI CMOS","author":"qazi","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"877","DOI":"10.1109\/JSSC.2005.845564","article-title":"A 130-nm 0.9 V 66-MHz 8-Mb (256 K$\\,\\times \\,$32) local SONOS embedded flash EEPROM","volume":"40","author":"seo","year":"2005","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013763"},{"key":"ref12","first-page":"428","article-title":"Bitline-capacitance-cancelation sensing scheme with 11 ns read latency and maximum read throughput of 2.9 GB\/s in 65 nm embedded flash for automotive","author":"jefremow","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"212","article-title":"40 nm embedded SG-MONOS flash macros for automotive with 160 MHz random access for code and endurance over 10 M cycles for data","author":"kono","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","first-page":"200","article-title":"A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random access time and 160 ns MLC-access capability","author":"sheu","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","first-page":"210","article-title":"A 4 Mb conductive-bridge resistive memory with 2.3 GB\/s read-through and 216 MB\/s program throughput","author":"otsuka","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","first-page":"434","article-title":"A 0.5 V 4 Mb logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low voltage current-mode sensing scheme with 45 ns random read time","author":"chang","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2297417"},{"key":"ref18","first-page":"42","article-title":"A 0.13 $\\mu {\\hbox{m}} $ 8 Mb logic based CuSiO resistive memory with self-adaptive yield enhancement and operation for power reduction","author":"xue","year":"2012","journal-title":"Proc Symp VLSI Tech"},{"key":"ref19","first-page":"260","article-title":"A 0.13 $\\mu{\\rm m}$ 64 Mb multi-layered conductive metal-oxide memory","author":"chevallier","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.829399"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2192661"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.210039"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2011.5783209"},{"key":"ref6","first-page":"230","article-title":"A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated active vmin-enhancement assist circuitry","author":"karl","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","first-page":"424","article-title":"A 45 nm self-aligned-contact process 1 Gb NOR flash with 5 MB\/s program speed","author":"javanifard","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"254","article-title":"A 64 Mb SRAM in 32 nm high-k metal-gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements","author":"pilo","year":"2011","journal-title":"Proc Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref8","first-page":"230","article-title":"A 1 Gb 2 GHz embedded DRAM in 22 nm tri-gate CMOS technology","author":"hamzaoglu","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"316","article-title":"A 20 nm 112 Mb SRAM in high-k metal-gate with assist circuitry for low-leakage and low-Vmin applications","author":"chang","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"38","article-title":"Value creation in SOC\/MCU applications by embedded nonvolatile memory evolutions","author":"hatanaka","year":"2007","journal-title":"Proc IEEE Asia Solid-State Circuits Conf (A-SSCC)"},{"key":"ref9","article-title":"A 28 nm 256 Kb 6T-SRAM with 280 mV improvement in VMIN using a dual-split-control assist scheme","author":"chang","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176866"},{"key":"ref20","first-page":"432","article-title":"An 8 Mb multi-layered cross-point ReRAM macro with 443 MB\/s write throughput","author":"kawahara","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","first-page":"338","article-title":"A 16 Gb ReRAM with 200 MB\/s write and 1 GB\/s read in 27 nm technology","author":"fackenthal","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","first-page":"210","article-title":"A 130.7 ${\\rm mm}^{2}$ 2-layer 32 Gb ReRAM memory device in 24 nm technology","author":"liu","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","first-page":"31.6.1","article-title":"High-K metal gate contact RRAM (CRRAM) in pure 28 nm CMOS logic process","author":"shen","year":"2012","journal-title":"IEEE Int Electron Devices Meeting (IEDM) Dig Tech Papers"},{"key":"ref23","first-page":"332","article-title":"Embedded 1 Mb ReRAM in 28 nm CMOS with 0.27-to-1 V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme","author":"chang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","first-page":"216","article-title":"Time-differential sense amplifier for sub-80 mV bitline voltage embedded STT-MRAM in 40 nm CMOS","author":"jefremow","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","first-page":"206","article-title":"An offset tolerant current-sampling-based sense amplifier for sub-100 nA-cell-current nonvolatile memory","author":"chang","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7307914\/07244257.pdf?arnumber=7244257","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,23]],"date-time":"2025-08-23T00:58:11Z","timestamp":1755910691000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7244257\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":30,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2472601","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,11]]}}}