{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T18:30:25Z","timestamp":1782930625525,"version":"3.54.5"},"reference-count":55,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/jssc.2015.2473667","type":"journal-article","created":{"date-parts":[[2015,9,14]],"date-time":"2015-09-14T18:40:32Z","timestamp":1442256032000},"page":"2678-2691","source":"Crossref","is-referenced-by-count":56,"title":["A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop"],"prefix":"10.1109","volume":"50","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0895-1700","authenticated-orcid":false,"given":"Salvatore","family":"Levantino","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"Marucci","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"Marzin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea","family":"Fenaroli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carlo","family":"Samori","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2023945"},{"key":"ref33","first-page":"189","article-title":"An inductor-less injection-locked PLL with 1\/2- and 1\/4-integral sub-harmonic locking in 90 nm CMOS","author":"lee","year":"2012","journal-title":"IEEE Radio Frequency Integrated Circuits (RFIC) Symp Dig"},{"key":"ref32","first-page":"336","article-title":"An all-digital clock generator using a fractionally injection-locked oscillator in 65 nm CMOS","author":"park","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref31","first-page":"52","article-title":"A pulse-position-modulation phase-noise-reduction technique for a 2-to-16 GHz injection-locked ring oscillator in 20 nm CMOS","author":"chien","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref30","first-page":"266","article-title":"A 0.0066 ${\\hbox{mm}}^{2}$ 780 $\\mu\\hbox{W}$ fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique","author":"deng","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref37","author":"da dalt","year":"2007","journal-title":"Theory and Implementation of Digital Bang-bang Frequency Synthesizers for High Speed Serial Data Communications"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571808"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217856"},{"key":"ref28","first-page":"414","article-title":"A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing","author":"lee","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227609"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2284651"},{"key":"ref2","first-page":"139","article-title":"A 2.2 GHz sub-sampling PLL with 0.16 psrms jitter and $-125 ~\\hbox{dBc}\/\\hbox{Hz}$ in-band phase noise at 700 $\\mu\\hbox{W}$ loop-components power","author":"gao","year":"2010","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits and Systems II Express Briefs"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1980.1094619"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2296195"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2321200"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2015816"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348311"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746232"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016701"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"ref51","first-page":"94","article-title":"A 0.1-${\\rm f}_{ref}$ BW 1 GHz fractional-N PLL with FIR embedded phase-interpolator-based noise filtering","author":"jee","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref55","first-page":"252","article-title":"A 0.048 ${\\hbox{mm}}^{2}$ 3 mW synthesizable fractional-N PLL with a soft injection-locking technique","author":"deng","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref54","first-page":"190","article-title":"A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter","author":"liang","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref53","first-page":"260","article-title":"A 1.22 ps integrated-jitter 0.25-to-4 GHz fractional-N ADPLL in 16 nm FinFet CMOS","author":"tsai","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref52","article-title":"A 4.25 GHz&#x2013;4.75 GHz calibration-free fractional-N ring PLL using hybrid phase\/current-mode phase interpolator with 13.2 dB phase-noise improvement","author":"nandwana","year":"2014","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804339"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804340"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831802"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917372"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref15","first-page":"466","article-title":"A 4.6 GHz MDLL with $-46~\\hbox{dBc}$ reference spur and aperture position tuning","author":"ali","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref16","first-page":"188","article-title":"A 0.45 V 423 nW 3.2 MHz multiplying DLL with leakage-based oscillator for ultra-low-power sensor platforms","author":"jee","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.585289"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.876206"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273836"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2325556"},{"key":"ref5","first-page":"362","article-title":"A 2.3 GHz fractional-N dividerless phase-locked loop with $-112~\\hbox{dBc}\/\\hbox{Hz}$ In-band phase noise","author":"huang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252515"},{"key":"ref7","first-page":"370","article-title":"A 2.4-to-5.3 GHz dual-core CMOS VCO with concentric 8-shaped coils","author":"fanori","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487795"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2283758"},{"key":"ref46","first-page":"272","article-title":"A 20-to-1000 MHz $\\pm 14~{\\rm ps}$ peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65 nm CMOS","author":"elkholy","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021086"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822896"},{"key":"ref47","first-page":"268","article-title":"A 0.012 ${\\hbox{mm}}^{2}$ 3.1 mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider","author":"liu","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/4.735535"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268514"},{"key":"ref44","first-page":"254","article-title":"A 0.026 ${\\hbox{mm}}^{2}$ 5.3 mW 32-to-2000 MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter","author":"jang","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref43","first-page":"360","article-title":"A 1.7 GHz MDLL-based fractional-N frequency synthesizer with 1.4 ps RMS integrated jitter and 3 mW power using a 1 b TDC","author":"marucci","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7307914\/07265103.pdf?arnumber=7265103","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:59:02Z","timestamp":1642003142000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7265103\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":55,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2473667","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,11]]}}}