{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:09:09Z","timestamp":1761581349887},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/jssc.2015.2475122","type":"journal-article","created":{"date-parts":[[2015,9,24]],"date-time":"2015-09-24T18:48:23Z","timestamp":1443120503000},"page":"2625-2634","source":"Crossref","is-referenced-by-count":15,"title":["A 3.12 pJ\/bit, 19\u201327 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery"],"prefix":"10.1109","volume":"50","author":[{"given":"Zheng-Hao","family":"Hong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yao-Chia","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Zen","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842863"},{"key":"ref11","first-page":"28","article-title":"A 32 Gb\/s wireline receiver with a low-frequency equalizer, CTLE and 2-Tap DFE in 28 nm CMOS","author":"parikh","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585951"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2364271"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.760368"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001876"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348556"},{"key":"ref17","first-page":"28","article-title":"32Gb\/s data-interpolator receiver with 2-tap DFE in 28 nm CMOS","author":"doi","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","first-page":"412","article-title":"A 3.1 mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28 nm CMOS","author":"bhardwaj","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref19","first-page":"1","article-title":"22.8 A 24-to-35 Gb\/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13 $\\mu$m SiGe BiCMOS","author":"tsunoda","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref27","first-page":"272","article-title":"An 11 Gb\/s 2.4 mW half-rate sampling 2-tap DFE receiver in 65 nm CMOS","author":"rylyakov","year":"2007","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2173387"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914290"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.808920"},{"key":"ref8","first-page":"277","article-title":"A 3.12 pJ\/bit, 19–27 Gbps receiver with 2 tap-DFE embedded clock and data recovery","author":"hong","year":"2014","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref7","first-page":"1","article-title":"A 4 $\\times$ 40 Gb\/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering","author":"hossain","year":"2014","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176951"},{"key":"ref9","first-page":"272","article-title":"An 11 Gb\/s 2.4 mW half-rate sampling 2-tap DFE receiver in 6S nm CMOS","author":"rylyakov","year":"2007","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref1","first-page":"42","article-title":"A 0.94 mW\/Gb\/s 22 Gb\/s 2-tap partial-response DFE receiver in 40 nm LP CMOS","author":"jung","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2299273"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705374"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.568834"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.494195"},{"key":"ref23","author":"razavi","year":"2003","journal-title":"Design of Integrated Circuits for Optical Communications"},{"key":"ref26","first-page":"92","article-title":"A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel","author":"soh","year":"2002","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.557648"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7307914\/07275066.pdf?arnumber=7275066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:59:03Z","timestamp":1642003143000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7275066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":27,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2475122","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,11]]}}}