{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:52:43Z","timestamp":1774720363367,"version":"3.50.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T00:00:00Z","timestamp":1448928000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/jssc.2015.2475160","type":"journal-article","created":{"date-parts":[[2015,9,30]],"date-time":"2015-09-30T18:46:44Z","timestamp":1443638804000},"page":"2870-2879","source":"Crossref","is-referenced-by-count":46,"title":["A 4.5 mW CT Self-Coupled <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\Delta\\Sigma$<\/tex><\/formula> Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation"],"prefix":"10.1109","volume":"50","author":[{"given":"Chen-Yen","family":"Ho","sequence":"first","affiliation":[]},{"given":"Cong","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Chi-Lun","family":"Lo","sequence":"additional","affiliation":[]},{"given":"Hung-Chieh","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Tze-Chien","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Yu-Hsin","family":"Lin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"182","article-title":"A 14b 23 MS\/s 48 mW resetting $\\Sigma\\Delta$<\/tex><\/ref_formula> ADC with 87 dB SFDR 11.7b ENOB & 0.5 mm $^{2}$<\/tex> <\/ref_formula> area","author":"lee","year":"2008","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008051"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"351","DOI":"10.1109\/JSSC.2007.914263","article-title":"A power optimized continuous-time $\\Delta\\Sigma$<\/tex><\/ref_formula> ADC for audio applications","volume":"43","author":"pavan","year":"2008","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref13","year":"2010","journal-title":"Operating circuit with RC calibration and RC calibration method"},{"key":"ref14","first-page":"244","article-title":"A 1.9 $\\mu\\hbox{W}$<\/tex> <\/ref_formula> 4.4 fJ\/conversion-step 10b 1 MS\/s charge-redistribution ADC","author":"van elzakker","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2453953"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032624"},{"key":"ref17","first-page":"172","article-title":"A 1.2 V 2 MHz BW 0.084 mm $^2$<\/tex><\/formula> CT ADC with 97.7 dBc THD and 80 dB DR using low-latency DEM","author":"huang","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref18","first-page":"268","article-title":"A 28 fJ\/conv-step CT $\\Delta\\Sigma$<\/tex> <\/ref_formula> modulator with 78 dB DR and 18 MHz BW in 28 nm CMOS using a highly digital multibit quantizer","author":"shu","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164302"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274852"},{"key":"ref27","first-page":"478","article-title":"A 84 dB SNDR 100 kHz bandwidth low-power single op-amp third-order $\\Delta\\Sigma$<\/tex> <\/ref_formula> modulator consuming 140 $\\mu\\hbox{W}$<\/tex> <\/ref_formula>","author":"perez","year":"2011","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"104","article-title":"A 97.3 dB SNR, 600 kHz BW, 31 mW multibit continuous time $\\Delta\\Sigma$<\/tex> <\/ref_formula> ADC","author":"bandyopadhyay","year":"2014","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref6","first-page":"42","article-title":"A 2.8 mW $\\Delta\\Sigma$<\/tex> <\/ref_formula> ADC with 83 dB DR and 1.92 MHz BW using FIR outer feedback and TIA-based integrator","author":"gealow","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref5","first-page":"60","article-title":"A 75.1 dB SNDR 840 MS\/s CT $\\Delta\\Sigma$<\/tex><\/ref_formula> modulator with 30 MHz bandwidth and 46.4 fJ\/conv FoM in 55 nm CMOS","author":"lo","year":"2013","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","first-page":"492","article-title":"A 3 mW 74 dB SNR 2 MHz CT $\\Delta\\Sigma$<\/tex><\/ref_formula> ADC with a tracking-ADC-quantizer in 0.13 $\\mu\\hbox{m}$<\/tex> <\/ref_formula> CMOS","author":"d\ufffdrrer","year":"2005","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2475160"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022298"},{"key":"ref9","first-page":"160","article-title":"A 10 MHz BW 50 fJ\/conv. continuous time $\\Delta\\Sigma$<\/tex><\/ref_formula> modulator with high-order single Opamp integrator using optimization-based design method","author":"matsukawa","year":"2012","journal-title":"IEEE Symp VLSI Circuits Dig"},{"key":"ref1","first-page":"478","article-title":"A 5 mW CT $\\Delta\\Sigma$<\/tex> <\/ref_formula> ADC with embedded 2nd-order active filter and VGA achieving 82 dB DR in 2 MHz BW","author":"rajan","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref20","article-title":"A 69.8 dB SNDR 3rd-order continuous time delta-sigma modulator with a ultimate low power tuning system for a worldwide digital TV-receiver","author":"matsukawa","year":"2010","journal-title":"Proc IEEE CICC"},{"key":"ref22","first-page":"276","article-title":"A 6.3 $\\mu\\hbox{W}$<\/tex><\/ref_formula> 20b incremental zoom-ADC with 6 ppm INL and 1 $\\mu\\hbox{V}$<\/tex> <\/ref_formula> offset","author":"chae","year":"2013","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","author":"murmann","year":"0","journal-title":"ADC Performance Survey 1997?2014"},{"key":"ref24","first-page":"385","article-title":"A 280 $\\mu\\hbox{W}$<\/tex> <\/ref_formula> audio continuous-time $\\Delta\\Sigma$<\/tex> <\/ref_formula> modulator with 103 dB DR and 102 dB A-Weighted SNR","author":"sukumaran","year":"2013","journal-title":"IEEE Asian Solid-State Circuits Conf (A-SSCC)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IPEC.2012.6522672"},{"key":"ref26","first-page":"1","article-title":"A 1 V 350 $\\mu\\hbox{W}$<\/tex> <\/ref_formula> 92 dB SNDR 24 kHz $\\Delta\\Sigma$<\/tex> <\/ref_formula> modulator in 0.18 $\\mu\\hbox{m}$<\/tex> <\/ref_formula> CMOS","author":"liu","year":"2010","journal-title":"Proc IEEE Asian Solid State Circuits Conf (A-SSCC)"},{"key":"ref25","first-page":"320","article-title":"A 110 $\\mu\\hbox{W}$<\/tex> <\/ref_formula> single bit audio continuous-time oversampled converter with 92.5 dB dynamic range","author":"pavan","year":"2009","journal-title":"Proc European Solid State Circuits Conf (ESSCIRC)"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7336577\/07284711.pdf?arnumber=7284711","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:45:51Z","timestamp":1642005951000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7284711\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":27,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2475160","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,12]]}}}