{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:20:54Z","timestamp":1771698054989,"version":"3.50.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T00:00:00Z","timestamp":1454284800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Institute for Information and Communications Technology Promotion IITP"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/jssc.2015.2494365","type":"journal-article","created":{"date-parts":[[2015,11,10]],"date-time":"2015-11-10T19:59:08Z","timestamp":1447185548000},"page":"391-400","source":"Crossref","is-referenced-by-count":23,"title":["A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC"],"prefix":"10.1109","volume":"51","member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"ref11","first-page":"252","article-title":"A 0.048 mm2 3 mW synthesizable fractional-N PLL with a soft injection-locking technique","author":"deng","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028753"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076591"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref15","first-page":"268","article-title":"A 0.012 mm2 3.1 mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider","author":"liu","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref16","first-page":"416","article-title":"A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation","author":"kao","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2209809"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2259031"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273836"},{"key":"ref4","first-page":"9","article-title":"A 1.6–880 MHz synthesizable ADPLL in 0.13 um CMOS","author":"chang","year":"0","journal-title":"Proc IEEE Int Symp VLSI Des Autom Test (VLSI-DAT)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2007.4488528"},{"key":"ref6","first-page":"250","article-title":"A 0.032 mm2 3.1 mW synthesized pixel clock generator with 30 ps$_{\\text{rms}}$ integrated jitter and 10-to-630 MHz DCO tuning range","author":"kim","year":"0","journal-title":"IEEE Int Solid-State Conf Dig Tech Papers"},{"key":"ref5","first-page":"1","article-title":"An all-digital PLL synthesized from a digital standard cell library in 65 nm CMOS","author":"park","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2013.6569537"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2013.6815331"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826333"},{"key":"ref9","first-page":"266","article-title":"A 0.0066 mm2 780 uW fully synthesizable PLL with a current-output DAC and an interpolative phase coupled oscillator using edge-injection technique","author":"deng","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807398"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7398196\/7323794.pdf?arnumber=7323794","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:47:51Z","timestamp":1642006071000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7323794\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":19,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2494365","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,2]]}}}