{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,24]],"date-time":"2026-10-24T06:37:30Z","timestamp":1792823850549,"version":"4.5.0"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/jssc.2015.2511164","type":"journal-article","created":{"date-parts":[[2016,1,22]],"date-time":"2016-01-22T16:37:59Z","timestamp":1453480679000},"page":"845-859","source":"Crossref","is-referenced-by-count":21,"title":["A 2.7 mW\/Channel 48\u20131000 MHz Direct Sampling Full-Band Cable Receiver"],"prefix":"10.1109","volume":"51","member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032497"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2012.6176959"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2011.5746273"},{"key":"ref4","first-page":"124","article-title":"A 22-mW 7 b 1.3-GS\/s pipeline ADC with 1-bit\/stage folding converter architecture","volume-title":"Proc. Symp. VLSI Circuits","author":"Yamase","year":"2011"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164961"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185192"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2012.6243801"},{"key":"ref8","first-page":"464","article-title":"An 11 b 3.6 GS\/s TI SAR ADC in 65nm CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers","author":"Janssen","year":"2013"},{"key":"ref9","first-page":"92","article-title":"A 5.4 GS\/s 12 b 500mW pipeline ADC in 28nm CMOS","volume-title":"Proc. Symp. VLSI Circuits","author":"Wu","year":"2013"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252518"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2259013"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757481"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361339"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2015.7063127"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063130"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063129"},{"key":"ref17","volume-title":"ADC Performance Survey 19972015","author":"Murmann"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.894307"},{"key":"ref19","first-page":"292","article-title":"A direct sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS","volume-title":"Proc. Symp. VLSI Circuits","author":"Janssen","year":"2011"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2011.6044978"},{"key":"ref21","first-page":"192","article-title":"An 8.5mW, 0.07mm2 ADPLL in 28nm CMOS with sub-ps resolution TDC and<230fs rms jitter","volume-title":"Proc. Symp. VLSI Circuits","author":"Shen","year":"2013"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977324"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039530"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055386"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176995"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/81.915383"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2253407"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063035"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2063630"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2012.6176992"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7446371\/7389971.pdf?arnumber=7389971","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,10,24]],"date-time":"2026-10-24T05:50:06Z","timestamp":1792821006000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7389971\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":31,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2015.2511164","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}