{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,27]],"date-time":"2025-11-27T06:35:14Z","timestamp":1764225314022},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Ministry of Science and Technology and Mediatek Inc.","award":["MOST 103-2622-E-002-034"],"award-info":[{"award-number":["MOST 103-2622-E-002-034"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/jssc.2016.2519391","type":"journal-article","created":{"date-parts":[[2016,2,15]],"date-time":"2016-02-15T19:10:03Z","timestamp":1455563403000},"page":"821-831","source":"Crossref","is-referenced-by-count":51,"title":["A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques"],"prefix":"10.1109","volume":"51","member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157259"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231354"},{"key":"ref12","first-page":"94","article-title":"Bang&#x2013;bang digital PLLs at 11 and 20\ufffdGHz with sub-200\ufffdfs integrated jitter for high-speed serial communication applications","author":"rylyakov","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658505"},{"key":"ref14","first-page":"31","article-title":"PLL\/DLL system noise analysis for low-jitter clock synthesizer design","author":"kim","year":"0","journal-title":"Proc Int Symp Circuits and Syst"},{"key":"ref15","author":"chatfield","year":"1991","journal-title":"The Analysis of Time Series An Introduction"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2220502"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268514"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2013.2273732"},{"key":"ref28","first-page":"139","article-title":"A 2.2\ufffdGHz sub-sampling PLL with 0.16 psrms jitter and &#x2013;125 dBc\/Hz in-band phase noise at 700\ufffd?W loop-components power","author":"gao","year":"0","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.806248"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"807","DOI":"10.1109\/4.845184","article-title":"A low-noise phase-locked loop design by loop bandwidth optimization","volume":"35","author":"lim","year":"2000","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757335"},{"key":"ref29","first-page":"270","article-title":"A 2.4\ufffdGHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO","author":"huang","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2423793"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.819124"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1137","DOI":"10.1109\/4.859502","article-title":"A low-noise fast-lock phase-locked loop with adaptive bandwidth control","volume":"35","author":"lee","year":"2000","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref9","first-page":"98","article-title":"A 570 fsrms integrated-jitter ring-VCO-based 1.21\ufffdGHz PLL with hybrid loop","author":"sai","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027507"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2083110"},{"key":"ref22","author":"razavi","year":"2012","journal-title":"RF Microelectronics"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883197"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2173395"},{"key":"ref23","author":"schreier","year":"2005","journal-title":"Understanding Delta-Sigma Data Converters"},{"key":"ref26","author":"razavi","year":"1995","journal-title":"Principles of Data Conversion System Design"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435691"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7446371\/7407308.pdf?arnumber=7407308","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:43:07Z","timestamp":1642005787000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7407308\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":29,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2519391","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}