{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T16:18:46Z","timestamp":1775146726595,"version":"3.50.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2016,4,1]],"date-time":"2016-04-01T00:00:00Z","timestamp":1459468800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF 0964606"],"award-info":[{"award-number":["CCF 0964606"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["CCF 1419949"],"award-info":[{"award-number":["CCF 1419949"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/jssc.2016.2519396","type":"journal-article","created":{"date-parts":[[2016,3,14]],"date-time":"2016-03-14T18:09:01Z","timestamp":1457978941000},"page":"908-918","source":"Crossref","is-referenced-by-count":28,"title":["A 3\u201310 fJ\/conv-step Error-Shaping Alias-Free Continuous-Time ADC"],"prefix":"10.1109","volume":"51","author":[{"given":"Sharvil","family":"Patil","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alin","family":"Ratiu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominique","family":"Morche","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yannis","family":"Tsividis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"626","article-title":"An ECG Recording front-end with continuous-time level-crossing sampling","volume":"8","author":"yongjia","year":"0","journal-title":"IEEE Trans Biomed Circuits Syst"},{"key":"ref11","author":"steele","year":"1975","journal-title":"Delta Modulation Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917500"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIECI.1979.351615"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2295977"},{"key":"ref15","author":"murmann","year":"2015","journal-title":"ADC Performance Survey 1997–2014"},{"key":"ref16","first-page":"266","article-title":"0.0058\ufffd${\\text{mm}}^2$ 7.0 ENOB 24 MS\/s 17 fJ\/conv. threshold configuring SAR ADC with source voltage shifting and interpolation technique","author":"yoshioka","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref17","first-page":"264","article-title":"A 1-V, 8 b, 40 MS\/s, 113\ufffd?W charge-recycling SAR ADC with a 14\ufffd?W asynchronous controller","author":"tsai","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref18","first-page":"242","article-title":"A 150 MS\/s 133\ufffd?W 7 b ADC in 90\ufffdnm digital CMOS using a comparator-based asynchronous binary-search sub-ADC","author":"plas","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908770"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2336532"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005456"},{"key":"ref6","first-page":"160","article-title":"A 3–10 fJ\/conv-step 0.0032\ufffd${\\text{mm}}^2$ error-shaping alias-free asynchronous ADC","author":"patil","year":"0","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2203459"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1981.1094872"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2262738"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007438"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2056012"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199179"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/4\/7446371\/7433385-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/7446371\/07433385.pdf?arnumber=7433385","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:55:51Z","timestamp":1649444151000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7433385\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":19,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2016.2519396","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,4]]}}}